Method and apparatus for reducing multipath distortion

Abstract

Abstract For every TDMA block the receiver operation starts with a forward processing procedure and operates on received samples in a first-in first-served order. A sync word detector 32a (see FIG. 4 ) ensures the correct TDMA frame timing and starts the equalizer training. Detected data is stacked in a decision buffer 46. An adaptive equalizer 34a outputs a decision error signal that is used to generate a latch-type loss-of-lock flag. Without loss-of-lock, the receiver works through to the last data symbol and the frame processing is finished. Forward processing is halted and the receiver switches to a backward processing branch if the receiver loses lock midway through the data block. The backward processing branch processes received samples from the input buffer 30 in reverse order. The sync word detector 32b detects the reverse trailing sync word (SYNC #2) and recovers the TDMA symbol timing. The receiver then trains the equalizer and starts data processing in a reverse mode. The detected data is then stacked in the decision buffer 46, starting from Nth symbol. The reverse loss-of-lock detector works the same as the forward loss-of-lock detector, however the control logic is modified such that backward processing works until either detected data overwrites a portion of the forward-processed data, or a loss-of-lock is declared. In the former case, the frame processing is finished. In the latter case, the midpoint between the two loss-of-lock points is calculated and, if needed, both processes are enabled toward the midpoint.

Inventors

• 👤 Chun-Meng Su
• 👤 Chanchai Poonpol
• 👤 George M. Peponides

Bibliographic Details