Patent US5430711A successfully refreshed from Google Patents.
US5430711A
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US
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Group modulator
Assignee: NTT Inc
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Filing: 1994-02-25
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Granted: 1995-07-04
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Expires: 2014-02-25
Abstract
Abstract A group modulator provided a plurality of digitally modulated signals with frequency division multiplex, having a time division multiplexer (11) for multiplexing a plurality of input data (#l through #n). A mapping circuit (12) provides an I-channel signal and a Q-channel signal according to a pattern of the multiplexed signal and the modulation system. A pulse shaping circuit (13) restricts bandwidth of the I-channel signal and the Q-channel signal. A frequency shift circuit (14) shifts frequency of the I-channel signal and the Q-channel signal by the frequency defined by the carrier control signal (i) for each input data. An accumulator (21,22) accumulates each of the I-channel signal and the Q-channel signal of the output of the frequency shift circuit (14) during a predetermined period (T). A D/A converter (31, 32) converts the output of the accumulator from digital form to analog form. A low pass filter (41, 42) is provided at the output of the D/A converter. A quadrature modulator (5) modulates carrier frequency (f c ) with quadrature modulation according to the I-channel signal and the Q-channel signal at the output of the low pass filter. A multiplicity control (6) controls multiplicity in the time division multiplexer (11) according to an external multiplicity signal.
Inventors
- 👤 Yoshifumi Yamada
- 👤 Tadashi Shibato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:01
CPC Classifications
H; H04; H04J; H04J1/00; H04J1/02; H04J1/06; H04J4/00; H04J4/005
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
173 words
A group modulator for providing a plurality of frequency division multiplexed modulated signals having different carrier frequency from one another relating to a plurality of input digital data comprising: a time division multiplexer for effecting time division multiplex of input digital data; a mapping circuit for assigning amplitude and phase for each pattern of the time dimension multiplexed input digital signal to provide I-channel signal and Q-channel signal according to a modulation system which modulates said input digital data; a pulse shaping circuit for restricting bandwidth of output of said mapping circuit; a frequency shift circuit receiving an external carrier control signal so that the frequency of said output of said pulse shaping circuit is shifted by the frequency defined by said carrier control signal; an accumulator for accumulating output of said frequency shift circuit during a predetermined period; a digital-to-analog converter for converting output of said accumulator from digital form to analog form; and a modulator for modulating output of said digital-to-analog converter to provide frequency division multiplexed modulated high frequency signal.
Claim 2
Dependent Claim
173 words
A group modulator for providing a plurality of frequency division multiplexed modulated signals having different carrier frequency from one another relating to a plurality of input digital data comprising: a time division multiplexer for effecting time division multiplex of input digital data; a mapping circuit for assigning amplitude and phase for each pattern of the time dimension multiplexed input digital signal to provide I-channel signal and Q-channel signal according to a modulation system which modulates said input digital data; a pulse shaping circuit for restricting bandwidth of output of said mapping circuit; a frequency shift circuit receiving an external carrier control signal so that the frequency of said output of said pulse shaping circuit is shifted by the frequency defined by said carrier control signal; an accumulator for accumulating output of said frequency shift circuit during a predetermined period; a digital-to-analog converter for converting output of said accumulator from digital form to analog form; and a modulator for modulating output of said digital-to-analog converter to provide frequency division multiplexed modulated high frequency signal.
Claim 3
Dependent Claim
33 words
A group modulator according to claim 1, wherein said modulator is a quadrature modulator, and said mapping circuit provides the I-channel signal and Q-channel signal having phase difference by 90° for quadrature modulation.
Claim 4
Dependent Claim
30 words
A group modulator according to claim 1, wherein said digital-to-analog converter has a latch circuit to keep an input signal to the level at the initial stage of the conversion.
Claim 5
Dependent Claim
23 words
A group modulator according to claim 1, wherein a low pass filter is provided between output of said digital-to-analog converter and said modulator.
Claim 6
Dependent Claim
43 words
A group modulator according to claim 1, wherein a multiplicity control is provided so that a number of multiplicity in said time division multiplexer is adjustably controlled according to a multiplicity signal which is applied to said multiplicity control from an outside circuit.
Claim 7
Dependent Claim
36 words
A group modulator according to claim 1, wherein said modulator is a frequency converter, and a bandpass filter is provided at output of said frequency converter to remove undesirable side band generated in said frequency converter.
Claim 8
Dependent Claim
19 words
A group modulator according to claim 5, wherein multiplicity is adjusted according to amount of traffic of input data.
Claim 9
Dependent Claim
52 words
A group modulator according to claim 1, wherein said frequency shift circuit is implemented by a plurality of digital multipliers each providing product of input signal of said frequency shift circuit and instantaneous value of said shift frequency, and an adder for providing sum of outputs of two of said digital multipliers.
Claim 10
Dependent Claim
50 words
A group modulator according to claim 1, wherein said frequency shift circuit is implemented by a plurality of ROM's which store product of input signal of said frequency shift circuit and instantaneous value of said shift frequency, and an adder for providing sum of outputs of two of said ROM's.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |