Patent US5430673A successfully refreshed from Google Patents.
US5430673A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buried bit line ROM with low bit line resistance
Assignee: United Microelectronics Corp
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Filing: 1993-07-14
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Granted: 1995-07-04
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Expires: 2013-07-14
Abstract
Abstract A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. Theis reduces bit line sheet resistance and increases the punch through voltage between adjacent bit lines.
Inventors
- 👤 Gary Hong
- 👤 Chen-Chiu Hsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:17
CPC Classifications
H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
74 words
A buried bit line for use in either of a ROM and an EPROM memory array, comprising: a semiconductor substrate having a trench formed therein, insulation material covering a portion of walls of said trench said insulation material not covering at least an upper portion of the walls, and heavily doped material in said trench and contacting said substrate at the portion of the walls of said trench not covered by said insulation material.
Claim 2
Dependent Claim
74 words
A buried bit line for use in either of a ROM and an EPROM memory array, comprising: a semiconductor substrate having a trench formed therein, insulation material covering a portion of walls of said trench said insulation material not covering at least an upper portion of the walls, and heavily doped material in said trench and contacting said substrate at the portion of the walls of said trench not covered by said insulation material.
Claim 3
Dependent Claim
27 words
The buried bit line of claim 1 wherein said substrate is silicon, said insulation material is SiO 2 , and said heavily doped material is doped polysilicon.
Claim 4
Dependent Claim
21 words
The buried bit line of claim 1 wherein a bottom surface of said trench is not covered with said insulation material.
Claim 5
Dependent Claim
101 words
A memory cell comprising: a semiconductor substrate having first and second spaced apart trenches formed therein; insulation material covering a portion of walls of said trenches, at least an upper portion of the walls not being covered with the insulation material; a heavily doped material deposited in said trenches and in contact with said substrate to form source and drain regions; a gate insulating layer formed on said substrate, said gate insulating layer being thicker in the portions over said trenches than in the portion over a channel between said trenches; and a conducting layer formed over said gate insulating layer.
Claim 6
Dependent Claim
101 words
A memory cell comprising: a semiconductor substrate having first and second spaced apart trenches formed therein; insulation material covering a portion of walls of said trenches, at least an upper portion of the walls not being covered with the insulation material; a heavily doped material deposited in said trenches and in contact with said substrate to form source and drain regions; a gate insulating layer formed on said substrate, said gate insulating layer being thicker in the portions over said trenches than in the portion over a channel between said trenches; and a conducting layer formed over said gate insulating layer.
Claim 7
Dependent Claim
48 words
The memory cell of claim 4 wherein: said substrate is silicon, said insulation material on said walls of said trenches is SiO 2 , said heavily doped material in said trenches is doped polysilicon, said gate insulating layer is formed from oxide, and said conducting layer is polysilicon.
Claim 8
Independent Claim
70 words
A method for forming a buried bit line for a memory array, comprising the steps of; a) forming a trench in a semiconductor substrate; b) depositing an insulating material in said trench; c) removing a portion of said insulating material so at least a an upper portion of the trench is exposed; and d) placing a heavily doped material in said trench for contacting said exposed portion of said wall.
Claim 9
Independent Claim
70 words
A method for forming a buried bit line for a memory array, comprising the steps of; a) forming a trench in a semiconductor substrate; b) depositing an insulating material in said trench; c) removing a portion of said insulating material so at least a an upper portion of the trench is exposed; and d) placing a heavily doped material in said trench for contacting said exposed portion of said wall.
Claim 10
Dependent Claim
34 words
The method of claim 6 wherein the conductive material includes dopant and further comprising the step of diffusing dopant from said heavily doped material into said substrate through said exposed portion of said wall.
Claim 11
Dependent Claim
21 words
The method of claim 6 wherein said substrate is silicon and said step of forming a trench is performed by etching.
Claim 12
Dependent Claim
13 words
The method of claim 8 wherein said insulating material is SiO 2 .
Claim 13
Dependent Claim
17 words
The method of claim 9 wherein said removing step comprises etching and then overetching said insulating material.
Claim 14
Dependent Claim
24 words
The method of claim 7 wherein said heavily doped material is doped polysilicon and wherein impurities in said polysilicon are diffused into said substrate.
Claim 15
Dependent Claim
23 words
The method of claim 11 further comprising the step of depositing an oxide layer and a polysilicon layer on top of said trench.
Claim 16
Dependent Claim
28 words
The method of claim 6, wherein the step of removing further includes removing a portion of said insulating material so a bottom portion of the trench is exposed.
Claim 17
Dependent Claim
76 words
A buried bit line for use in a memory array comprising: (a) a semiconductor substrate having a trench formed therein, the trench having walls and a bottom surface; (b) insulation material covering a portion of said trench so that at least an upper portion the of the walls is not covered; and (c) a conducting material deposited in said trench and contacting said substrate at the portion of the trench not covered by said insulation material.
Claim 18
Dependent Claim
76 words
A buried bit line for use in a memory array comprising: (a) a semiconductor substrate having a trench formed therein, the trench having walls and a bottom surface; (b) insulation material covering a portion of said trench so that at least an upper portion the of the walls is not covered; and (c) a conducting material deposited in said trench and contacting said substrate at the portion of the trench not covered by said insulation material.
Claim 19
Dependent Claim
25 words
The buried bit line of claim 14, wherein the portion of the trench not covered by insulation material includes the bottom surface of the trench.
References Cited (Backward Citations)
US4222062A
Cited
US5017977A
Cited
JPS63207171A
Cited
US4912535A
Cited
JPH02113571A
Cited
US5278438A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |