Semiconductor accelerometer and method of its manufacture

Claim 2

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a first surface; (b) forming an insulator layer on said first surface of said support substrate, said first surface of said support substrate having a first portion the entirety of which is disposed beneath and contacts said insulator layer formed thereon; (c) forming a semiconductor layer on said insulating layer; (d) selectively forming an etch-masking layer on said semiconductor layer, said etch-masking layer having a masking pattern that overlies said first portion of said first surface of said support substrate, said masking pattern masking a first, accelerometer mass portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer, which join said first accelerometer mass portion of said semiconductor layer with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and expose a plurality of fourth portions of said semiconductor layer disposed between said first accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, arm portion joins said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transverse to said lengthwise dimension, and wherein said first accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said respective third, arm portion of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches said fourth portions of said semiconductor layer exposed by said plurality of first apertures down to said insulator layer therebeneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said insulator layer exposed by the etching of said semiconductor layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer, so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to said second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 3

A method according to claim 1, wherein step (c) further comprises introducing conductive impurities into said third, arm portions of said semiconductor layer thereby forming respective piezo-resistive regions therein.

Claim 4

A method according to claim 1, wherein step (d) includes selectively forming in Said etch-masking layer at least one aperture overlying said first, accelerometer mass portion of said semiconductor layer, so that, in step (e), said first etchant etches through that portion of said first, accelerometer mass portion of said semiconductor layer exposed by said at least one aperture and, in step (f), said insulator layer is exposed to and etched by said second etchant by way of the etched-through portion of said first, accelerometer portion of said semiconductor layer.

Claim 5

A method according to claim 3, wherein said at least one aperture includes a plurality of apertures.

Claim 6

A method according to claim 1, wherein said plurality of third, arm portions of said semiconductor layer comprises at least three arm portions of said semiconductor layer.

Claim 7

A method according to claim 1, wherein the entirety of said first portion of said first surface of said support substrate upon which said insulator layer is formed is a planar surface.

Claim 8

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a planar surface; (b) forming an insulator layer on said planar surface of said support substrate, said planar surface of said support substrate having a first portion the entirety of which is disposed beneath and contacts a first portion of said insulator layer formed thereon, and such that the thickness of a second portion of said insulator layer surrounding said first portion thereof is the same as the thickness of said first portion of said insulator overlying said first portion of said planar surface of said support substrate; (c) forming a semiconductor layer on said first and second portions of said insulating layer, such that each of first and second regions of said semiconductor layer respectively overlying said first and second portions of said insulator layer has the same thickness; (d) selectively forming an etch-masking layer on said semiconductor layer, said etch-masking layer having a masking pattern that overlies said first region of said semiconductor layer and thereby said first portion of said planar surface of said support substrate, said masking pattern masking a first, accelerometer mass portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer, which join said first accelerometer mass portion of said semiconductor layer with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and expose a plurality of fourth portions of said semiconductor layer disposed between said first accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, arm portion joins said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transverse to said lengthwise dimension, and wherein said first accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said respective third, arm portion of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches said fourth portions of said semiconductor layer exposed by said plurality of first apertures down to said insulator layer therebeneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said insulator layer exposed by the etching of said semiconductor layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer, so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to said second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 9

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a planar surface; (b) forming an insulator layer on said planar surface of said support substrate, said planar surface of said support substrate having a first portion the entirety of which is disposed beneath and contacts a first portion of said insulator layer formed thereon, and such that the thickness of a second portion of said insulator layer surrounding said first portion thereof is the same as the thickness of said first portion of said insulator overlying said first portion of said planar surface of said support substrate; (c) forming a semiconductor layer on said first and second portions of said insulating layer, such that each of first and second regions of said semiconductor layer respectively overlying said first and second portions of said insulator layer has the same thickness; (d) selectively forming an etch-masking layer on said semiconductor layer, said etch-masking layer having a masking pattern that overlies said first region of said semiconductor layer and thereby said first portion of said planar surface of said support substrate, said masking pattern masking a first, accelerometer mass portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer, which join said first accelerometer mass portion of said semiconductor layer with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and expose a plurality of fourth portions of said semiconductor layer disposed between said first accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, arm portion joins said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transverse to said lengthwise dimension, and wherein said first accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said respective third, arm portion of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches said fourth portions of said semiconductor layer exposed by said plurality of first apertures down to said insulator layer therebeneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said insulator layer exposed by the etching of said semiconductor layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer, so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to said second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 10

A method according to claim 7, wherein step (c) further comprises introducing conductive impurities into said third, arm portions of said semiconductor layer thereby forming respective piezo-resistive regions therein.

Claim 11

A method according to claim 7, wherein step (d) includes selectively forming in said etch-masking layer at least one aperture overlying said first, accelerometer mass portion of said semiconductor layer, so that, in step (e), said first etchant etches through that portion of said first, accelerometer mass portion of said semiconductor layer exposed by said at least one aperture and, in step (f), said insulator layer is exposed to and etched by said second etchant by way of the etched-through portion of said first, accelerometer portion of said semiconductor layer.

Claim 12

A method according to claim 9, wherein said at least one aperture includes a plurality of apertures.

Claim 13

A method according to claim 7, wherein said plurality of third, arm portions of said semiconductor layer comprises at least three arm portions of said semiconductor layer.

Claim 14

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a first surface, said first surface of said support substrate having a first conductive layer formed thereon; (b) forming an insulator layer on said first conductive layer on said first surface of said support substrate, said first surface of said support substrate and said first conductive layer formed thereon having a first portion the entirety of which is disposed beneath and contacts said insulator layer formed thereon; (c) providing a semiconductor layer having a second conductive layer formed thereon and attaching said second conductive layer to a side of said insulator layer opposite to that contacting said first conductive layer so that said first and second conductive layers contact opposite sides of said insulator layer; (d) selectively forming an edge-masking layer on said semiconductor layer, said edge-masking layer having a masking pattern that overlies said first, portion of said first surface of said support substrate, said masking pattern masking a first accelerometer mass portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer, which join said first accelerometer mass portion of said semiconductor layer, with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and expose a plurality of portions of said semiconductor layer disposed between said first accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, aim portions join said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transverse to said lengthwise dimension, and wherein said first accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said third, arm portions of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches through said second conductive layer exposed by said first apertures of said etch-masking layer and through said fourth portions of said semiconductor layer exposed by said plurality of first apertures down to said insulator layer therebeneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said insulator layer exposed by the etching of said semiconductor layer and said second conductive layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 15

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a first surface, said first surface of said support substrate having a first conductive layer formed thereon; (b) forming an insulator layer on said first conductive layer on said first surface of said support substrate, said first surface of said support substrate and said first conductive layer formed thereon having a first portion the entirety of which is disposed beneath and contacts said insulator layer formed thereon; (c) providing a semiconductor layer having a second conductive layer formed thereon and attaching said second conductive layer to a side of said insulator layer opposite to that contacting said first conductive layer so that said first and second conductive layers contact opposite sides of said insulator layer; (d) selectively forming an edge-masking layer on said semiconductor layer, said edge-masking layer having a masking pattern that overlies said first, portion of said first surface of said support substrate, said masking pattern masking a first accelerometer mass portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer, which join said first accelerometer mass portion of said semiconductor layer, with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and expose a plurality of portions of said semiconductor layer disposed between said first accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, aim portions join said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transverse to said lengthwise dimension, and wherein said first accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said third, arm portions of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches through said second conductive layer exposed by said first apertures of said etch-masking layer and through said fourth portions of said semiconductor layer exposed by said plurality of first apertures down to said insulator layer therebeneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said insulator layer exposed by the etching of said semiconductor layer and said second conductive layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 16

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a first conductive layer formed on a planar surface thereof; (b) forming an insulator layer on said first conductive layer on said planar surface of said support substrate, said first conductive layer on said planar surface of said support substrate having a first portion the entirety of which is disposed beneath and contacts a first portion of said insulator layer formed thereon, and such that the thickness of a second portion of said insulator layer surrounding said first portion thereof is the same as the thickness of said first portion of said insulator layer overlying said first portion of said first conductive layer formed on said planar surface of said support substrate; (c) forming a second conductive layer on a semiconductor layer and attaching said second conductive layer to a side of said insulator layer opposite to that contacting said first conductive layer such that first and second regions of said semiconductor layer, having the same thickness, respectively overlie said first and second portions of said insulator layer; (d) selectively forming an etch-masking layer on said semiconductor layer, said etch-masking layer having a masking pattern that overlies said first region of said semiconductor layer and thereby said first portion of said first conductive layer on said planar surface of said support substrate, said masking pattern masking a first, accelerometer mask portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer which joins said first, accelerometer mass portion of said semiconductor layer with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and a plurality of fourth portions of said semiconductor layer disposed between said first, accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, arm portion joins said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transversed to said lengthwise dimension, and wherein said first, accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said respective third, arm portion of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches said second conductive layer and said semiconductor layer exposed by the masking pattern of said etch-masking layer down to said insulator layer beneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said,insulator layer exposed by the etching of said second conductive layer and said semiconductor layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer, so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to said second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.

Claim 17

A process for manufacturing a cantilevered semiconductor accelerometer device comprising the steps of: (a) providing a support substrate having a first conductive layer formed on a planar surface thereof; (b) forming an insulator layer on said first conductive layer on said planar surface of said support substrate, said first conductive layer on said planar surface of said support substrate having a first portion the entirety of which is disposed beneath and contacts a first portion of said insulator layer formed thereon, and such that the thickness of a second portion of said insulator layer surrounding said first portion thereof is the same as the thickness of said first portion of said insulator layer overlying said first portion of said first conductive layer formed on said planar surface of said support substrate; (c) forming a second conductive layer on a semiconductor layer and attaching said second conductive layer to a side of said insulator layer opposite to that contacting said first conductive layer such that first and second regions of said semiconductor layer, having the same thickness, respectively overlie said first and second portions of said insulator layer; (d) selectively forming an etch-masking layer on said semiconductor layer, said etch-masking layer having a masking pattern that overlies said first region of said semiconductor layer and thereby said first portion of said first conductive layer on said planar surface of said support substrate, said masking pattern masking a first, accelerometer mask portion of said semiconductor layer, masking a second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer, and masking a plurality of third, arm portions of said semiconductor layer which joins said first, accelerometer mass portion of said semiconductor layer with said second, support portion of said semiconductor layer, spaced apart therefrom, and wherein said masking pattern further has a plurality of first apertures which overlie and a plurality of fourth portions of said semiconductor layer disposed between said first, accelerometer mass portion of said semiconductor layer and said second, support portion of said semiconductor layer, spaced apart therefrom, and between said third, arm portions, and wherein a respective third, arm portion of said semiconductor layer has a first, lengthwise dimension in a direction along which said respective third, arm portion joins said first accelerometer mass portion and said second, support portion of said semiconductor layer, and a lateral dimension transversed to said lengthwise dimension, and wherein said first, accelerometer mass portion of said semiconductor layer has a lateral dimension greater than the lateral dimension of said respective third, arm portion of said semiconductor layer; (e) exposing the structure resulting from step (d) to a first etchant which etches said second conductive layer and said semiconductor layer exposed by the masking pattern of said etch-masking layer down to said insulator layer beneath; (f) exposing the structure resulting from step (e) to a second etchant which etches said,insulator layer exposed by the etching of said second conductive layer and said semiconductor layer in step (e) and also beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer, so as to leave said first, accelerometer mass portion supported by said plurality of third, arm portions of said semiconductor layer in cantilever fashion to said second, support portion of said semiconductor layer which surrounds and is spaced apart from said first, accelerometer mass portion of said semiconductor layer; and (g) leaving said third, arm portions of said semiconductor layer spaced apart from one another by apertures through said fourth portions of said semiconductor layer and leaving said support substrate exposed by said apertures through said fourth portions of said semiconductor layer and that portion of said insulator layer that has been removed beneath said first, accelerometer mass portion and said plurality of third, arm portions of said semiconductor layer.