Method of making single bit erase flash EEPROM

Claim 1

A method of manufacture of an EEPROM device on a semiconductor substrate comprising: forming a tunnel oxide layer over said substrate, forming a floating gate layer above said tunnel oxide layer, forming a first dielectric layer over said floating gate layer, forming a control gate layer over said first dielectric layer, forming a second dielectric layer over said control gate layer, patterning a pair of stacks of said floating gate layer, said first dielectric layer, said control gate layer and said second dielectric layer, forming a doping mask for source/drain regions on said substrate, ion implanting an array of five source/drain regions including three source drain regions at the base of said stacks to form two EEPROM transistors and two source/drain regions of a select transistor spaced laterally from said stacks, forming dielectric spacer structures covering the sides of said stacks, forming a select gate layer covering said dielectric spacer structures and the substrate, and forming select transistor gate electrodes extending over said dielectric spacer structures by patterning said select gate layer wherein said source/drain regions of the select transistor are spaced laterally from said stacks and said dielectric spacer structures.

Claim 2

A method of manufacture of an EEPROM device on a semiconductor substrate comprising: forming a tunnel oxide layer over said substrate, forming a floating gate layer above said tunnel oxide layer, forming a first dielectric layer over said floating gate layer, forming a control gate layer over said first dielectric layer, forming a second dielectric layer over said control gate layer, patterning a pair of stacks of said floating gate layer, said first dielectric layer, said control gate layer and said second dielectric layer, forming a doping mask for source/drain regions on said substrate, ion implanting an array of five source/drain regions including three source drain regions at the base of said stacks to form two EEPROM transistors and two source/drain regions of a select transistor spaced laterally from said stacks, forming dielectric spacer structures covering the sides of said stacks, forming a select gate layer covering said dielectric spacer structures and the substrate, and forming select transistor gate electrodes extending over said dielectric spacer structures by patterning said select gate layer wherein said source/drain regions of the select transistor are spaced laterally from said stacks and said dielectric spacer structures.

Claim 14

A method of manufacture of an EEPROM device on a semiconductor substrate comprising: forming a tunnel oxide layer over said substrate, forming a floating gate layer comprising a material selected from polysilicon and a polycide above said tunneling oxide layer, masking said first floating gate layer in the pattern of transverse bars by etching into transverse bar patterns, forming an interconductor, first dielectric layer over said floating gate layer, forming a control gate layer comprising a material selected from polysilicon and a polycide over said first dielectric layer, forming a second dielectric layer over said control gate layer, patterning a pair of stacks of said floating gate layer, said first dielectric layer, said control gate layer and said second dielectric layer, forming a doping mask for source/drain regions on said substrate, ion implanting an array of five source/drain regions including three source/drain regions at the base of said stacks to form two EEPROM transistors and two source/drain region of a select transistor spaced laterally form said stacks, forming a blanket dielectric spacer layer over said stacks, source/drain regions, and the substrate etching said dielectric spacer layer to form spacers covering the sides of said stacks, while etching away exposed portions of said tunnel oxide exposing portions of said substrate, forming a gate oxide layer over said exposed portion of said substrate, forming a select gate layer comprising a polysilicon layer or a polycide layer extending over said gate oxide layer and said spacers, and forming select transistor gate electrodes extending over said gate layer and spacers by pattering the select gate layer wherein said source/drain regions of the select transistor are laterally spaced from said stacks and spacers.

Claim 15

A method of manufacture of an EEPROM device on a semiconductor substrate comprising: forming a tunnel oxide layer over said substrate, forming a floating gate layer comprising a material selected from polysilicon and a polycide above said tunneling oxide layer, masking said first floating gate layer in the pattern of transverse bars by etching into transverse bar patterns, forming an interconductor, first dielectric layer over said floating gate layer, forming a control gate layer comprising a material selected from polysilicon and a polycide over said first dielectric layer, forming a second dielectric layer over said control gate layer, patterning a pair of stacks of said floating gate layer, said first dielectric layer, said control gate layer and said second dielectric layer, forming a doping mask for source/drain regions on said substrate, ion implanting an array of five source/drain regions including three source/drain regions at the base of said stacks to form two EEPROM transistors and two source/drain region of a select transistor spaced laterally form said stacks, forming a blanket dielectric spacer layer over said stacks, source/drain regions, and the substrate etching said dielectric spacer layer to form spacers covering the sides of said stacks, while etching away exposed portions of said tunnel oxide exposing portions of said substrate, forming a gate oxide layer over said exposed portion of said substrate, forming a select gate layer comprising a polysilicon layer or a polycide layer extending over said gate oxide layer and said spacers, and forming select transistor gate electrodes extending over said gate layer and spacers by pattering the select gate layer wherein said source/drain regions of the select transistor are laterally spaced from said stacks and spacers.