Process for producing a very high density mask ROM

Claim 1

A process for producing a very high density mask ROM device having NAND FET devices and memory cells, in a semiconductor substrate with a first conductivity type background ion impurity comprising: forming an insulating layer on the surface of said substrate; implanting second conductivity type impurity ions into said substrate adjacent the top surface to form a depletion layer; depositing a nitride layer over said insulating layer; patterning said nitride layer to form a plurality of parallel spaced lines; removing the exposed this insulating layer between the spaced lines; forming a first gate oxide layer on the surface of the substrate between the spaced lines; forming a first doped layer of polycrystalline silicon over said spaced lines and first gate oxide layer with a thickness of at least as great as the thickness of the nitride layer; planarized etching the first layer of polycrystalline silicon to expose the top surfaces of the spaced lines of nitride; removing the spaced lines of nitride leaving parallel lines of polycrystalline silicon that constitute first gate electrodes, said first gate electrode lines each having a central depression; removing the exposed insulating layer between the first gate electrode lines, and an insulating layer on the surfaces of the first gate electrode lines; forming a second doped layer of polycrystalline silicon over the first gate electrode lines and second gate oxide; planarized etching the second layer of polycrystalline silicon to expose the top surfaces of the first gate electrode lines to form second gate electrode lines between the first gate electrode lines, each of second gate electrode lines having a central elongated depression; depositing, exposing, and developing a photoresist layer on the substrate that defines the code openings; implanting ions of a first impurity through the code openings with sufficient energy to penetrate the substrate beneath the central depressions of the first and second gate electrode lines providing self alignment of the implant; and removing the photoresist layer.