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US5428807A
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Method and apparatus for propagating exception conditions of a computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-06-17
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Granted: 1995-06-27
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Expires: 2013-06-17
Abstract
Abstract There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.
Inventors
- 👤 Francis X. McKeen
- 👤 Michael C. Adler
- 👤 Joel S. Emer
- 👤 Robert P. Nix
- 👤 David J. Sager
- 👤 P. Geoffrey Lowny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3842; G06F9/3863
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
299 words
An apparatus for propagating exception conditions of data manipulated by instructions of a computer system, comprising: a set of data registers for storing the data manipulated by the instructions of the computer system, each data register of said set of data registers being a source data register when used as a source of the data and each data register of said set of data registers being a destination data register when used as a destination of the data; a set of state registers for storing speculative states of the data manipulated by the instructions, there being a one-to-one association between each data register of said set of data registers and each state register of said set of state registers, each state register being a source state register if said data register associated with said state register is used as the source of the data and each state register being a destination state register if said data register associated with said state register is used as the destination of the data; means for grouping the instructions into a plurality of execution threads; a unique identification for each one of said plurality of execution threads; means for executing said plurality of execution threads in parallel in the computer; means, coupled to said set of state registers, for propagating said speculative states from said source state register to said destination state register, if the data stored in said source data register are used as the source for the destination dam register, and if the data stored in said source data register were subject to an exception condition while executing one of said plurality of execution threads; and means for propagating said unique identification of said one of said plurality of execution threads from said source state register to said destination state register.
Claim 2
Independent Claim
299 words
An apparatus for propagating exception conditions of data manipulated by instructions of a computer system, comprising: a set of data registers for storing the data manipulated by the instructions of the computer system, each data register of said set of data registers being a source data register when used as a source of the data and each data register of said set of data registers being a destination data register when used as a destination of the data; a set of state registers for storing speculative states of the data manipulated by the instructions, there being a one-to-one association between each data register of said set of data registers and each state register of said set of state registers, each state register being a source state register if said data register associated with said state register is used as the source of the data and each state register being a destination state register if said data register associated with said state register is used as the destination of the data; means for grouping the instructions into a plurality of execution threads; a unique identification for each one of said plurality of execution threads; means for executing said plurality of execution threads in parallel in the computer; means, coupled to said set of state registers, for propagating said speculative states from said source state register to said destination state register, if the data stored in said source data register are used as the source for the destination dam register, and if the data stored in said source data register were subject to an exception condition while executing one of said plurality of execution threads; and means for propagating said unique identification of said one of said plurality of execution threads from said source state register to said destination state register.
Claim 3
Dependent Claim
34 words
The apparatus as in claim 1 wherein each of said speculative states includes an exception flag for indicating if the data stored in said set of data registers were subject to said exception condition.
Claim 4
Dependent Claim
49 words
The apparatus as in claim 2 wherein said speculative states further includes a memory address, said memory address to enable a repeating execution of the instructions of said one of said plurality of execution threads if the data were subject to said exception condition to resolve said exception condition.
Claim 5
Dependent Claim
46 words
The apparatus as in claim 2 wherein said means for propagating includes an OR gate having inputs coupled to said set of state registers, said OR gate generating a propagate signal upon a detection of said exception flag in any of said set of state register.
Claim 6
Dependent Claim
41 words
The apparatus as in claim 4 further including means for writing the data stored in said set of data registers to a main memory while said repeating execution of the instructions of said one of the said plurality of execution threads.
Claim 7
Independent Claim
241 words
A method for propagating exception conditions of data manipulated by instructions of a computer system, comprising: storing, in a set of data registers, the data manipulated by the instructions of the computer system each data register of said set of data registers being a source data register when used as a source of the data and each data register being a destination data register when used as a destination the data; storing, in a set of state registers, speculative states of the data manipulated by the instructions, there being one data register associated with each state data register, and each state being a source state when said data register associated with said state register is the source of the data, and each state register being a destination state register when said data register associated with said state register is the destination of the data; grouping the instructions into a plurality of execution threads; a unique identification for each of said plurality of execution threads; executing said plurality of execution threads in parallel in the computer; propagating, said speculative states from said source state register to said destination state register, if the data stored in said source data register are used as the source for the data stored in said destination data registers, and if the dam stored in said source data register were subject to an exception condition while manipulated by the instructions of one of said plurality of execution threads.
Claim 8
Independent Claim
241 words
A method for propagating exception conditions of data manipulated by instructions of a computer system, comprising: storing, in a set of data registers, the data manipulated by the instructions of the computer system each data register of said set of data registers being a source data register when used as a source of the data and each data register being a destination data register when used as a destination the data; storing, in a set of state registers, speculative states of the data manipulated by the instructions, there being one data register associated with each state data register, and each state being a source state when said data register associated with said state register is the source of the data, and each state register being a destination state register when said data register associated with said state register is the destination of the data; grouping the instructions into a plurality of execution threads; a unique identification for each of said plurality of execution threads; executing said plurality of execution threads in parallel in the computer; propagating, said speculative states from said source state register to said destination state register, if the data stored in said source data register are used as the source for the data stored in said destination data registers, and if the dam stored in said source data register were subject to an exception condition while manipulated by the instructions of one of said plurality of execution threads.
Claim 9
Dependent Claim
39 words
The method as in claim 6 including the step of storing an exception flag with each of said speculative states, said exception flag to indicate if the data stored in said data register were subject to said exception condition.
Claim 10
Dependent Claim
54 words
The method as in claim 7 including the step of storing a memory address with each of said speculative states, said memory address to enable a repeating execution of the instructions of said one of said plurality of execution threads if the data were subject to said exception condition to resolve said exception condition.
Claim 11
Dependent Claim
38 words
The method as in claim 8 including the step of ORing the inputs received from said set of state registers to generate a propagate signal upon a detection of said exception flag in any of said state registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |