Distributed mechanism for the fast scheduling of shared objects and apparatus

Claim 1

In a multiprocessor environment wherein a plurality of processors are attached through a bussing system to a shared intelligent memory, said plurality of processors being interconnected via queuing operations performed through said shared intelligent memory, a distributed scheduling mechanism provided for coordinating and arbitrating processes, each process including a set of programmed elementary tasks to be performed by server or target processors upon request from a source processor handling source processes with a set of target processors working on the same queue defining a process group, said processes communicating through said queue(s) by using messages, said scheduling mechanism including: a) defining within said shared memory for each said queues a set of memory locations connected to operate as a FIFO data message queue dedicated to all server processors of a process group; b) said shared intelligent memory memorizing for each process group, a signalling processor list SPL containing references of the server processors which need to dequeue data messages from said queue and attaching said list to the FIFO data message queue; c) enabling a given source process to enqueue a data message into said FIFO data message queue; d) monitoring, with said intelligent memory, the status of said FIFO data message queue and, if said queue was empty prior to enqueuing the data message, generating a signal E-NE signalling the transition of the queue content from empty to non-empty upon said enqueuing of a new data message; e) providing a scheduler mechanism within each server processor of the process group; f) providing a scheduler state table in each of the scheduler mechanism for listing at least one logical record address (LRA) of a FIFO data message queue and a state of the FIFO data message queue; g) said shared intelligent memory, transmitting said E-NE signal to all said server processors of said signalling processor list; h) upon receipt of said E-NE signal by the server processors, scheduling a given server processor through its dedicated scheduler mechanism to access the FIFO data message queue and dequeue from said data message queue a data message to be used by said server processor; and i) updating the FIFO data message queue state within the scheduler state table dedicated to each scheduler.