Patent US5272576A successfully refreshed from Google Patents.
Patent US5428741A successfully refreshed from Google Patents.
US5428741A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed image preprocessing system including a multi-purpose buffer for storing digital image data and data cropping means for selectively cropping the digital image data
Assignee: NCR Voyix Corp
•
Filing: 1993-07-26
•
Granted: 1995-06-27
•
Expires: 2013-07-26
Abstract
Abstract A system for use in image recognition applications to reduce the processing demands on the associated Host Computer thus allowing for greater system throughput. Compressed image data is transmitted over a Small Computer System Interface (SCSI) for storage in a Multi-Purpose Buffer. The data may decompressed, byte-swapped, byte-flipped, or may be passed through the system unmodified as directed by the Host Computer. A Video Compression-Expansion Processor can handle a variety of data compression formats and receives data from the Multi-Purpose Buffer. Processed data which matches preprogrammed sets of window coordinates can be selectively cropped and stored in multiple First-In-First-Out (FIFO) buffers by Cropper Controller circuitry. The processed and cropped data is then sent to the Host Computer through a Micro-Channel Architecture (MCA) Interface Controller for further recognition processing by the Host Computer. A high data throughput rate is achieved by synchronizing data transfer among the components of the preprocessing system by use of the Multi-Purpose Buffer and a data window storage mechanism.
Inventors
- 👤 Benedict C. M. Ho
- 👤 Thomas S. Craig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:14
CPC Classifications
G; G06; G06T; G06T9/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
203 words
A high speed digital image preprocessing system connected between a data link and a host computer interface bus, said high speed digital image preprocessing system comprising: a digital multi-purpose buffer for storing digital image data, said digital image data being comprised of a plurality of digital image words; a video processor connected to receive said digital image data from said digital multi-purpose buffer; a data link interface controller to direct a flow of said digital image data to and from said data link; a multi-purpose buffer controller for providing signals to control the flow of said digital image data between said digital multi-purpose buffer, said data link, said video processor, and said host computer interface bus; a data cropping controller connected to receive a plurality of preprogrammed window coordinates such that said digital image data processed by said video processor which matches the preprogrammed window coordinates is identified; a host computer interface means to direct the flow of said digital image data to and from said host computer interface bus; and a window data storage means connected to receive said identified digital image data from said video processor and connected to send said identified digital image data to said host computer interface bus.
Claim 2
Dependent Claim
203 words
A high speed digital image preprocessing system connected between a data link and a host computer interface bus, said high speed digital image preprocessing system comprising: a digital multi-purpose buffer for storing digital image data, said digital image data being comprised of a plurality of digital image words; a video processor connected to receive said digital image data from said digital multi-purpose buffer; a data link interface controller to direct a flow of said digital image data to and from said data link; a multi-purpose buffer controller for providing signals to control the flow of said digital image data between said digital multi-purpose buffer, said data link, said video processor, and said host computer interface bus; a data cropping controller connected to receive a plurality of preprogrammed window coordinates such that said digital image data processed by said video processor which matches the preprogrammed window coordinates is identified; a host computer interface means to direct the flow of said digital image data to and from said host computer interface bus; and a window data storage means connected to receive said identified digital image data from said video processor and connected to send said identified digital image data to said host computer interface bus.
Claim 3
Dependent Claim
67 words
The system as recited in claim 1 wherein said digital multi-purpose buffer is connected between said data link and said video processor such that said multi-purpose buffer stores the digital image data received from said data link and supplies the digital image data to the video processor as requested by the video processor, thus allowing for a continuous processing of said image data by the video processor.
Claim 4
Dependent Claim
85 words
The system as recited in claim 1 wherein said mutli-purpose buffer controller provides a first shared direct memory access (DMA) data channel to transfer said digital image data between said multi-purpose buffer and said data link and between said multi-purpose buffer and said host computer interface, and additionally provides a second DMA data channel to transfer said digital image data between said multi-purpose buffer and said video processor simultaneously with the transfer of said digital image data between said multi-purpose buffer and said data link.
Claim 5
Dependent Claim
35 words
The system as recited in claim 3 wherein said video processor provides a third direct memory access data channel to transfer said digital image data from said video processor to said window data storage means.
Claim 6
Dependent Claim
39 words
The system as recited in claim 1 wherein said video processor compresses and decompresses said digital image data received from said digital multi-purpose buffer and is connected to transfer said digital image data to said window data storage means.
Claim 7
Dependent Claim
28 words
The system as recited in claim 4 wherein said video processor includes means for passing said digital image data received thereby directly to said window data storage means.
Claim 8
Dependent Claim
50 words
The system as recited in claim 1 wherein: each of said digital data words includes a high byte and a low byte; and said multi-purpose buffer controller includes means for byte ordering said digital image words by juxtaposing the high byte with the low byte of said digital image word.
Claim 9
Dependent Claim
58 words
The system as recited in claim 1 wherein: each of said digital data words includes at least one byte, said byte comprising a plurality of bits; and said multi-purpose buffer includes means for byte flipping said digital image words by juxtaposing the bits of each byte of said digital image word about the center of each said byte.
Claim 10
Dependent Claim
40 words
The system as recited in claim 1 wherein said multi-purpose buffer controller includes means for generating signals to said host computer interface means to indicate when said digital image buffer is empty and when the digital image buffer is full.
Claim 11
Dependent Claim
37 words
The system as recited in claim 1 wherein said window data storage means includes means for generating signals to said data cropping controller to indicate when said window data storage means is empty, full, and half full.
Claim 12
Dependent Claim
21 words
The system as recited in claim 1 wherein said data cropping controller receives said preprogrammed window coordinates which overlap in area.
Claim 13
Dependent Claim
31 words
The system as recited in claim 11 wherein said preprogrammed window coordinates are at least one bit by sixteen bits but no larger than the maximum capacity of said multi-purpose buffer.
Claim 14
Dependent Claim
42 words
The system as recited in claim 1 wherein said window data storage means is connected to receive said digital image data cropped by said data cropping controller, said window data storage means further comprises a plurality of independent first-in first-out buffers (FIFO).
Claim 15
Dependent Claim
36 words
The system as recited in claim 13 further comprising a forth and fifth direct memory access data channel to transfer said digital image data from each said independent FIFO to said host computer interface means respectively.
Claim 16
Dependent Claim
18 words
The system as recited in claim 1 wherein said data link comprises a Small Computer System Interface (SCSI).
Claim 17
Dependent Claim
64 words
The system as recited in claim 1 wherein said multi-purpose buffer controller provides signals to control the flow of said digital image data between said digital multi-purpose buffer, said data link, said video processor, and said host computer interface bus to facilitate bi-directional data flow to and from said multi-purpose buffer at rates supporting maximum transfer rates of said data link and video processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |