US5426767A
Expired / Lapsed
US
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Method for distinguishing between a 286-type central processing unit and a 386-type central processing unit
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-12-18
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Granted: 1995-06-20
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Expires: 2010-12-18
Abstract
Abstract A method is disclosed for distinguishing between the Intel 80386 and 80286 CPUs. Bits 12, 13, and 14 of the 386 flags word in the real mode are always zero in the 286 architecture and cannot be set, but can be set to a one on the 386. The method includes the steps of attempting to set any of those bits and examining the results. A source code listing is attached.
Inventors
- 👤 William C. Crosswy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2289; G06F11/006; Y; Y10; Y10S; Y10S707/00; Y10S707/99931; Y10S707/99933; Y10S707/99936
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
121 words
A method for operating a CPU to determine its type, said CPU selected from a group including 386 type microprocessors and 286 type microprocessors, comprising the steps of: performing a load operation to the flags register of said CPU with a selected data word; and after said step of performing a load operation, testing a specified bit of the CPU's flags register, said specified bit being any of bits 12, 13 or 14, to determine if said specified bit was loaded with the corresponding bit in said selected data word as a result of said load operation or if said step of performing a load operation did not load said specified bit with the corresponding bit in said selected data word.
Claim 2
Independent Claim
121 words
A method for operating a CPU to determine its type, said CPU selected from a group including 386 type microprocessors and 286 type microprocessors, comprising the steps of: performing a load operation to the flags register of said CPU with a selected data word; and after said step of performing a load operation, testing a specified bit of the CPU's flags register, said specified bit being any of bits 12, 13 or 14, to determine if said specified bit was loaded with the corresponding bit in said selected data word as a result of said load operation or if said step of performing a load operation did not load said specified bit with the corresponding bit in said selected data word.
Claim 3
Dependent Claim
38 words
The method of claim 1, wherein said testing step comprises: copying the contents of said flags register into a second register after said performing step; and examining the bit of said second register corresponding to said specified bit.
Claim 4
Independent Claim
177 words
A method of operating an integrated circuit logic device to determine its type by executing a computer program, said logic device selected from a group of logic device types comprising a first type corresponding to 386-type microprocessors and a second type corresponding to 286-type microprocessors, said method comprising the steps of: performing a load operation to a flags register of said logic device with a selected data word, said flags register having a certain bit therein which is writable by said load operation for logic devices of the first type of said group of logic device types, and which is not writable by said load operation for logic devices of the second type of said group of logic device types; and testing said certain bit of said flags register to determine if said certain bit was written with the corresponding bit in said selected data word as a result of said load operation; wherein said logic device is identified as of said first type or of said second type based on the result of sail testing step.
Claim 5
Independent Claim
177 words
A method of operating an integrated circuit logic device to determine its type by executing a computer program, said logic device selected from a group of logic device types comprising a first type corresponding to 386-type microprocessors and a second type corresponding to 286-type microprocessors, said method comprising the steps of: performing a load operation to a flags register of said logic device with a selected data word, said flags register having a certain bit therein which is writable by said load operation for logic devices of the first type of said group of logic device types, and which is not writable by said load operation for logic devices of the second type of said group of logic device types; and testing said certain bit of said flags register to determine if said certain bit was written with the corresponding bit in said selected data word as a result of said load operation; wherein said logic device is identified as of said first type or of said second type based on the result of sail testing step.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |