Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor

Claim 2

In a data processing system incorporating a cache memory and a main memory, a method for predicting subsequent cache request addresses from historic cache miss addresses comprising: during the system hardware, firmware and software design procedure, performing the preliminary steps of: A) establishing a first in, first out miss stack for storing a plurality of cache miss addresses by employing at least a selected one of hardware, firmware and software design and implementation techniques; and B) establishing a predetermined precedence among a plurality of address patterns which may be matched during system operation; and, during system operation, performing the following steps within the system: C) waiting for a cache miss resulting from the absence in the cache of called information requested of the cache; D) when a cache miss occurs, placing the address of the absent called information onto the top of the miss stack; E) examining the miss stack for the presence of a plurality of predetermined address patterns among the cache miss addresses resident therein following step D); F) if a plurality of predetermined address patterns are not matched, returning to step C); and F) if a plurality of predetermined address patterns are matched: 1) following the predetermined precedence established in step B) to select a single address pattern for calculating a predictive address; 2) using the selected address pattern and at least one of the addresses in the miss stack to calculate a predictive address pointed to a signal group stored in the main memory; 3) prefetching into cache memory from the main memory the signal group identified by the predictive address; and 4) returning to step C).

Claim 3

Apparatus for developing a predictive address for prefetching signal groups, each identified by an address, from a main memory into a cache memory comprising: A) a first in, first out stack for storing a plurality of cache miss addresses representing successive cache misses; B) at least first and second pairs of subtraction circuit means, each said subtraction circuit means being coupled to receive a unique pair of addresses from said first in, first out stack and to issue a value representing the displacement therebetween; C) at least first and second comparator circuit means, each said first and second comparator circuit means being coupled to receive a pair of outputs from a corresponding pair of said subtraction circuit means and responsive to the presence of a match condition therebetween for issuing a prefetch enable logic signal; and D) predictive address development means adapted to combine a selected one of said cache miss addresses and displacement information appearing at one of said subtraction circuit means to obtain a predictive address, said predictive address development means including: 1) an adder circuit; 2) electronic switch means operatively disposed intermediate one input to said adder circuit and the output from one subtraction circuit of each pair thereof; and C) a priority encoder adapted to respond to the simultaneous presence of a plurality of compare conditions to provide control signals to said electronic switch means such that only one set of displacement information signals is applied to said adder circuit for combination with said selected one of said cache miss addresses to obtain said predictive address; whereby, the coordinated presence of said predictive address and said prefetch enable logic signal causes the signal group identified by said predictive address to be prefetched from said main memory into said cache memory.

Claim 4

Apparatus for developing a predictive address for prefetching signal groups, each identified by an address, from a main memory into a cache memory comprising: A) a first in, first out stack for storing a plurality of cache miss addresses representing successive cache misses; B) at least first and second pairs of subtraction circuit means, each said subtraction circuit means being coupled to receive a unique pair of addresses from said first in, first out stack and to issue a value representing the displacement therebetween; C) at least first and second comparator circuit means, each said first and second comparator circuit means being coupled to receive a pair of outputs from a corresponding pair of said subtraction circuit means and responsive to the presence of a match condition therebetween for issuing a prefetch enable logic signal; and D) predictive address development means adapted to combine a selected one of said cache miss addresses and displacement information appearing at one of said subtraction circuit means to obtain a predictive address, said predictive address development means including: 1) an adder circuit; 2) electronic switch means operatively disposed intermediate one input to said adder circuit and the output from one subtraction circuit of each pair thereof; and C) a priority encoder adapted to respond to the simultaneous presence of a plurality of compare conditions to provide control signals to said electronic switch means such that only one set of displacement information signals is applied to said adder circuit for combination with said selected one of said cache miss addresses to obtain said predictive address; whereby, the coordinated presence of said predictive address and said prefetch enable logic signal causes the signal group identified by said predictive address to be prefetched from said main memory into said cache memory.

Claim 5

The apparatus of claim 2 in which said selected one of said cache miss addresses employed to calculate said predictive address is the current cache miss address.