US5426646A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instantaneous bit-error-rate meter
Assignee: UNITED STATES OLF AMERICA NAVY, Secretary of
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Filing: 1992-06-25
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Granted: 1995-06-20
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Expires: 2012-06-25
Abstract
Abstract An instantaneous bit-error-rate meter provides an instantaneous, real-timeeading of bit-error-rate for digital communications data. Bit-error pulses are input into the meter and are first filtered in a buffer stage to provide input impedance matching and desensitization to pulse variations in amplitude, rise-time and pulse-width. The bit-error pulses are transformed into trigger signals for a timing pulse generator. The timing pulse generator generates timing pulses for each transformed bit-error pulse, and is calibrated to generate timing pulses having a preselected pulse width corresponding to the baud rate of the communications data. An integrator generates a voltage from the timing pulses that is representative of the bit-error-rate as a function of the data transmission rate. The integrated voltage is then displayed on a meter to indicate the bit-error-rate.
Inventors
- 👤 Robert A. Slack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; H; H04; H04L; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
121 words
An apparatus for indicating bit errors in digital communications data, said digital communications data having a data transmission rate, said bit errors being input to said apparatus as error pulses, said apparatus indicating said bit errors as a function of said data transmission, rate, said apparatus comprising: means for receiving said error pulses; means for generating timing pulses, a timing pulse being generated for each of said error pulses; means for setting a pulse width of said timing pulses according to said data transmission rate, such that said timing pulses become pulses width set timing pulses; means for generating voltage as a function of said pulse width set timing pulse; and means for displaying said voltage to represent bit error rate.
Claim 2
Independent Claim
121 words
An apparatus for indicating bit errors in digital communications data, said digital communications data having a data transmission rate, said bit errors being input to said apparatus as error pulses, said apparatus indicating said bit errors as a function of said data transmission, rate, said apparatus comprising: means for receiving said error pulses; means for generating timing pulses, a timing pulse being generated for each of said error pulses; means for setting a pulse width of said timing pulses according to said data transmission rate, such that said timing pulses become pulses width set timing pulses; means for generating voltage as a function of said pulse width set timing pulse; and means for displaying said voltage to represent bit error rate.
Claim 3
Dependent Claim
45 words
An apparatus according to claim 1 further including means for injecting said error pulses into said apparatus at a rate substantially equivalent to said data transmission rate and means for adjusting said means for displaying said voltage to indicate a 100 percent bit error rate.
Claim 4
Dependent Claim
16 words
An apparatus according to claim 1 in which said means for generating voltage includes an integrator.
Claim 5
Dependent Claim
28 words
An apparatus according to claim 3 in which said integrator has a time constant that is greater than said pulse width of said pulse width set timing pulses.
Claim 6
Independent Claim
152 words
An apparatus for indicating bit errors in digital communications data, said digital communications data having a data transmission rate, said bit errors being input to said apparatus as error pulses, said apparatus indicating said bit errors as a function of said data transmission rate, said apparatus comprising: means for receiving said error pulses; means for filtering said error pulses so that said error pulses are transformed into trigger pulses; means for generating timing pulses, one of said timing pulses being generated upon receipt of one of said trigger pulses; means for setting a pulse width of said timing pulses according to said data transmission rate, such that said timing pulses become pulse width set timing pulses; means for generating voltage proportionate to an integral of said pulse width set timing pulses; means for amplifying said voltage to generate an amplified voltage; and means for displaying said amplified voltage to represent said bit-error-rate.
Claim 7
Independent Claim
152 words
An apparatus for indicating bit errors in digital communications data, said digital communications data having a data transmission rate, said bit errors being input to said apparatus as error pulses, said apparatus indicating said bit errors as a function of said data transmission rate, said apparatus comprising: means for receiving said error pulses; means for filtering said error pulses so that said error pulses are transformed into trigger pulses; means for generating timing pulses, one of said timing pulses being generated upon receipt of one of said trigger pulses; means for setting a pulse width of said timing pulses according to said data transmission rate, such that said timing pulses become pulse width set timing pulses; means for generating voltage proportionate to an integral of said pulse width set timing pulses; means for amplifying said voltage to generate an amplified voltage; and means for displaying said amplified voltage to represent said bit-error-rate.
Claim 8
Dependent Claim
46 words
An apparatus according to claim 5 further including means for injecting said error pulses into said apparatus at a rate substantially equivalent to said data transmission rate and means for adjusting said means for displaying said amplified voltage to indicate a 100 percent bit error rate.
Claim 9
Dependent Claim
28 words
An apparatus according to claim 6 in which said integral has a time constant that is greater than said pulse width of said pulse width set timing pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |