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US5426596A
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Color signal correction circuit using a second-order correcting formula
Assignee: Fujitsu Ltd
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Filing: 1993-10-01
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Granted: 1995-06-20
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Expires: 2013-10-01
Abstract
Abstract An object of the present invention is to realize a color correction circuit according to a second order color correction formula in which capacities of memories and an operation time are further reduced. A color correction circuit includes three latches, four memories for dividedly storing correction values, and an adder. A first memory receives first and second color separation signals and a color selection signal as address signals. A second memory receives second and third color separation signals and a color selection signal as address signals. A third memory receives third and first color separation signals and the color selection signal as address signals. A value of a product term of the first and second color separation signals is included in the value of the first memory. A value of a product term of the second and third color separation signals is included in the value of the second memory. A value of a product term of the third and first color separation signals is included in the value of the third memory. Values of linear terms and square terms of respective color separation signals are included in memories to which related color separation signals are input.
Inventors
- 👤 Nobuo Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 00:41
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/46; H04N1/56; H04N1/60; H04N1/6016; H04N1/6019
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
279 words
A color signal correction circuit for correcting three digital color separation signals according to a second-order color correction formula having terms, comprising: first, second and third latches respectively holding said three digital color separation signals; a first memory receiving first and second color separation signals of said three digital color separation signals and a color selection signal as address signals, and outputting a first value, which is a sum of a first group of terms; a second memory receiving second and third color separation signals of said three digital color separation signals and said color selection signal as address signals, and outputting a second value, which is a sum of a second group of terms; a third memory receiving third and first color separation signals of said three digital color separation signals and said color selection signal as address signals, and outputting a third value, which is a sum of a third group of terms; and an adder outputting a sum of first, second, and third values received from said first, second and third memories, said first group of terms including the product of said first and second color separation signals in said second-order color correction formula, said second group of terms including the product of said second and third color separation signals in said second-order color correction formula, said third group of terms including the product of said third and first color separation signals in said second-order color correction formula, and values of linear terms and square terms of respective color separation signals in said second-order color correction formula being included in said output from first, second and third memories to which related color separation signals are input.
Claim 2
Dependent Claim
279 words
A color signal correction circuit for correcting three digital color separation signals according to a second-order color correction formula having terms, comprising: first, second and third latches respectively holding said three digital color separation signals; a first memory receiving first and second color separation signals of said three digital color separation signals and a color selection signal as address signals, and outputting a first value, which is a sum of a first group of terms; a second memory receiving second and third color separation signals of said three digital color separation signals and said color selection signal as address signals, and outputting a second value, which is a sum of a second group of terms; a third memory receiving third and first color separation signals of said three digital color separation signals and said color selection signal as address signals, and outputting a third value, which is a sum of a third group of terms; and an adder outputting a sum of first, second, and third values received from said first, second and third memories, said first group of terms including the product of said first and second color separation signals in said second-order color correction formula, said second group of terms including the product of said second and third color separation signals in said second-order color correction formula, said third group of terms including the product of said third and first color separation signals in said second-order color correction formula, and values of linear terms and square terms of respective color separation signals in said second-order color correction formula being included in said output from first, second and third memories to which related color separation signals are input.
Claim 3
Dependent Claim
36 words
A color signal correction circuit as set forth in claim 1, wherein said circuit comprises a fourth memory for outputting each constant term of said three digital color separation signals according to said color selection signal.
Claim 4
Dependent Claim
42 words
A color signal correction circuit as set forth in claim 1, wherein the number of bits of said second color separation signal input to said first memory is less than that of said second color separation signal input to said second latch.
Claim 5
Dependent Claim
42 words
A color signal correction circuit as set forth in claim 1, wherein the number of bits of said third color separation signal input to said second memory is less than that of said third color separation signal input to said third latch.
Claim 6
Dependent Claim
42 words
A color signal correction circuit as set forth in claim 1, wherein the number of bits of said first color separation signal input to said third memory is less than that of said first color separation signal input to said first latch.
Claim 7
Dependent Claim
38 words
A color signal correction circuit as set forth in claim 1, wherein said first, second and third memories are rewritable random access memories, and the contents of said rewritable random access memories are changeable from outside said circuit.
References Cited (Backward Citations)
JPS61111071A
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JPS61139166A
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JPH027671A
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JPH0244971A
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JPH0366288A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |