US5426385A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Double positive feedback loop precharge CMOS single-ended sense amplifier
Assignee: National Science and Technology Council
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Filing: 1994-06-07
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Granted: 1995-06-20
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Expires: 2014-06-07
Abstract
Abstract A single ended sense amplifier that not only preserves the high speed feature of the ordinary |V TP |, the threshold voltage of a PMOS transistor, but also eliminates the current leakage problem of conventional designs. The single-ended sense amplifier uses seven transistors and one phase clock instead of eleven transistors and two phase clocks as used in the prior art.
Inventors
- 👤 Fei-Pi Lai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/067
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
A double positive-feedback-loop pre-charge/pre-discharge single-ended sense amplifier controlled by a clock phase signal to trigger pre-charge/discharge in order to input a signal through an input terminal and output said signal through an output terminal; said single-ended sense amplifier comprising: a first MOS transistor having a source terminal to which a first voltage potential is applied, a gate terminal coupled to said clock phase signal, and a drain terminal coupled to said input terminal; a second MOS transistor having a source terminal to which a second voltage potential is applied, and a drain terminal coupled to said input terminal; a third MOS transistor having a source terminal to which said first voltage potential is applied, a gate terminal coupled to said input terminal, and a drain terminal coupled to a gate of said second MOS transistor; a fourth MOS transistor having a source terminal to which said second voltage potential is applied, a gate terminal coupled to an inverted clock phase signal, and a drain terminal coupled to said gate of said second MOS transistor; a fifth MOS transistor having a source terminal to which said second voltage potential is applied, a gate terminal coupled to said output terminal, and a drain terminal coupled to said gate of said second MOS transistor; an inverter having an input port coupled to said gate of said second MOS transistor and an output port coupled to said output terminal.
Claim 2
Dependent Claim
235 words
A double positive-feedback-loop pre-charge/pre-discharge single-ended sense amplifier controlled by a clock phase signal to trigger pre-charge/discharge in order to input a signal through an input terminal and output said signal through an output terminal; said single-ended sense amplifier comprising: a first MOS transistor having a source terminal to which a first voltage potential is applied, a gate terminal coupled to said clock phase signal, and a drain terminal coupled to said input terminal; a second MOS transistor having a source terminal to which a second voltage potential is applied, and a drain terminal coupled to said input terminal; a third MOS transistor having a source terminal to which said first voltage potential is applied, a gate terminal coupled to said input terminal, and a drain terminal coupled to a gate of said second MOS transistor; a fourth MOS transistor having a source terminal to which said second voltage potential is applied, a gate terminal coupled to an inverted clock phase signal, and a drain terminal coupled to said gate of said second MOS transistor; a fifth MOS transistor having a source terminal to which said second voltage potential is applied, a gate terminal coupled to said output terminal, and a drain terminal coupled to said gate of said second MOS transistor; an inverter having an input port coupled to said gate of said second MOS transistor and an output port coupled to said output terminal.
Claim 3
Dependent Claim
49 words
The single-ended sense amplifier as claimed in claim 1, wherein said first voltage potential is higher than said second voltage potential and said first MOS transistor and said third transistor are PMOS transistors, said second MOS transistor, said fourth MOS transistor, and said fifth MOS transistor are NMOS transistors.
Claim 4
Dependent Claim
23 words
The single ended sense amplifier as claimed in claim 1, wherein said inverter consists essentially of a PMOS transistor and an NMOS transistor.
Claim 5
Dependent Claim
23 words
The single ended sense amplifier as claimed in claim 2, wherein said inverter is composed of a PMOS transistor and a NMOS transistor.
References Cited (Backward Citations)
US4823031A
Cited
US4982363A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |