US5424668A
Expired / Lapsed
US
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Pulse duty ratio descrimination circuit
Assignee: Toshiba Corp
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Filing: 1993-11-10
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Granted: 1995-06-13
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Expires: 2013-11-10
Abstract
Abstract In a pulse duty ratio discrimination circuit for discriminating duty ratios of input signals by comparing a count value with a threshold value through means of counting, with a counter using clocks, a time period starting with a reference level changing point occurring every predetermined period in the input signal and ending with a level returning point, the present invention is characterized by a pulse duty ratio discrimination circuit that includes not only period determination means for determining the periods of the input signals by resetting the count value of the counter at the period of the input signal and by comparing actual count values for a plural number of count patterns of the counter established in advance, but also clock selection means for selecting the frequency of the clock based on a determination result of the period determination means.
Inventors
- 👤 Yoshiaki Kohsaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:07
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/32; G11B27/322; G11B27/324; H; H03; H03K; H03K5/00; H03K5/19; G11B2220/00; G11B2220/90; G11B2220/91
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
94 words
A pulse duty ratio discrimination circuit for discriminating duties of input signals comprising: means for counting a time interval of the input signal from a reference level changing point occurring every predetermined period of the input signal to a level returning point by using a clock; means for comparing a count value obtained by the counting means with a prescribed threshold value; means for determining a period of the input signals; and clock selection means responsive to the period determining means for selecting a specific clock having a frequency suitable to the comparing means.
Claim 2
Dependent Claim
94 words
A pulse duty ratio discrimination circuit for discriminating duties of input signals comprising: means for counting a time interval of the input signal from a reference level changing point occurring every predetermined period of the input signal to a level returning point by using a clock; means for comparing a count value obtained by the counting means with a prescribed threshold value; means for determining a period of the input signals; and clock selection means responsive to the period determining means for selecting a specific clock having a frequency suitable to the comparing means.
Claim 3
Dependent Claim
62 words
A pulse duty ratio discrimination circuit as claimed in claim 1, wherein the period determining means includes: means for resetting the count value obtained by the counting means at the period of the input signal, and second comparing means responding to the resetting means for comparing actual count values corresponding to a prescribed number of count patterns preset in the counting means.
Claim 4
Dependent Claim
68 words
A pulse duty ratio discrimination circuit as claimed in claim 2, wherein the resetting means includes: pattern generator means for selectively generating a set of pattern signals corresponding to the count value of the counting means, up/down counter means for controlling the clock selection means, and gate means for selectively activating the up/down counter means by logically responding to the pattern signals generated from the pattern generator means.
Claim 5
Dependent Claim
100 words
A circuit for determining a pulse duty ratio factor of an input pulse signal, the circuit comprising: a clock pulse generator; a counter for counting clock pulses generated during a pulse width of the input pulse signal; a comparator for comparing the number of counted pulses with a threshold value equivalent to a predetermined fraction of the number of counter pulses generated during one input pulse period, and generating a determination output on the basis of said comparison; means for determining the input pulse period; and means for adjusting the clock pulse frequency in response to the period thus determined.
Claim 6
Dependent Claim
100 words
A circuit for determining a pulse duty ratio factor of an input pulse signal, the circuit comprising: a clock pulse generator; a counter for counting clock pulses generated during a pulse width of the input pulse signal; a comparator for comparing the number of counted pulses with a threshold value equivalent to a predetermined fraction of the number of counter pulses generated during one input pulse period, and generating a determination output on the basis of said comparison; means for determining the input pulse period; and means for adjusting the clock pulse frequency in response to the period thus determined.
Claim 7
Dependent Claim
49 words
A circuit as claimed in claim 4, further comprising means for deriving from the number of counted pulses an indication as to whether the input pulse period lies within a given range, appropriate to the clock pulse frequency, and adjusting said frequency if the period lies outside said range.
Claim 8
Dependent Claim
124 words
A pulse duty ratio discrimination circuit for discriminating duties of input signals by comparing a count value with a threshold value by counting a time period from a reference level changing point occurring every predetermined period in the input signal to a level returning point with a counter by 6 using clocks, the pulse duty ratio discrimination circuit comprising: period determination means for determining the periods of the input signals by resetting the count value of the counter at the period of the input signal, and comparing actual count values for a plural number of count patterns of the counter established in advance; and clock selection means for selecting the frequency of the clock based on a determination result of the period determination means.
Claim 9
Dependent Claim
124 words
A pulse duty ratio discrimination circuit for discriminating duties of input signals by comparing a count value with a threshold value by counting a time period from a reference level changing point occurring every predetermined period in the input signal to a level returning point with a counter by 6 using clocks, the pulse duty ratio discrimination circuit comprising: period determination means for determining the periods of the input signals by resetting the count value of the counter at the period of the input signal, and comparing actual count values for a plural number of count patterns of the counter established in advance; and clock selection means for selecting the frequency of the clock based on a determination result of the period determination means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-12 | 1998-12-12 | 1999-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-12 | 2002-12-12 | 2003-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-12 | 2006-12-12 | 2007-06-13 | $7700.00 | Window Closed / Lapsed |