Method of making electrically programmable and erasable memory device with a depression

Claim 1

A method of forming an improved electrically programmable read only memory device having a lightly doped source region which partially underlies a floating gate and a surface depression in said lightly doped source region comprising the steps of: providing a semiconductor substrate having a dopant of a first type impurity; forming an insulating layer on the surface of the semiconductor substrate; forming an oxidation resistant masking layer over the insulating layer; forming openings in the oxidation resistant masking layer that define a field oxide layer and a first opening which defines the lightly doped source region; growing the field oxide in the openings that define the field oxide layer and forming a first oxide in said first opening; removing the oxidation resistant masking layer; forming a resist layer over the substrate surface with a second opening over said first opening; etching the first oxide that is exposed in said second opening thereby forming a depression in the substrate surface; implanting ions of a second conductivity type into the substrate through the second opening forming a lightly doped source region; removing the resist layer; removing the remaining insulating layer; forming a tunnel oxide layer on the exposed substrate; forming a floating gate on the tunnel oxide layer that at least partially overlaps said lightly doped source region; forming a gate insulation layer on the floating gate; forming a control gate over the floating gate; forming an ion implantation masking layer with openings which define the source and drain regions; implanting ions of a second type into said substrate to form source and drain regions; forming a dielectric layer over the control gate and substrate; and forming electrical contacts and metallurgy lines with passivation, and connecting the source, drain and control gate to form an electrically programmable memory device.

Claim 2

A method of forming an improved electrically programmable read only memory device having a lightly doped source region which partially underlies a floating gate and a surface depression in said lightly doped source region comprising the steps of: providing a semiconductor substrate having a dopant of a first type impurity; forming an insulating layer on the surface of the semiconductor substrate; forming an oxidation resistant masking layer over the insulating layer; forming openings in the oxidation resistant masking layer that define a field oxide layer and a first opening which defines the lightly doped source region; growing the field oxide in the openings that define the field oxide layer and forming a first oxide in said first opening; removing the oxidation resistant masking layer; forming a resist layer over the substrate surface with a second opening over said first opening; etching the first oxide that is exposed in said second opening thereby forming a depression in the substrate surface; implanting ions of a second conductivity type into the substrate through the second opening forming a lightly doped source region; removing the resist layer; removing the remaining insulating layer; forming a tunnel oxide layer on the exposed substrate; forming a floating gate on the tunnel oxide layer that at least partially overlaps said lightly doped source region; forming a gate insulation layer on the floating gate; forming a control gate over the floating gate; forming an ion implantation masking layer with openings which define the source and drain regions; implanting ions of a second type into said substrate to form source and drain regions; forming a dielectric layer over the control gate and substrate; and forming electrical contacts and metallurgy lines with passivation, and connecting the source, drain and control gate to form an electrically programmable memory device.

Claim 15

A method of forming an improved electrically erasable programmable read only memory device comprising the steps of: providing semiconductor substrate having a dopant of a first conductivity type; forming a first oxide region on the substrate; removing the first oxide forming a depression in the substrate surface; forming a lightly doped source region in the substrate below said depression region; forming a tunnel oxide layer on the substrate surface that fully overlies said lightly doped source; forming a floating gate on the tunnel oxide layer; forming a gate insulation layer on the floating gate; forming a control gate over the floating gate; forming spaced source and drain regions in the substrate separated by a channel region, with the source adjacent to the lightly doped source region, with the lightly doped source region adjacent to the channel region, and the channel region adjacent to the drain; forming a dielectric layer over the control gate and substrate; forming electrical contacts and metallurgy lines with passivation; and connecting the source, drain and control gate to form an electrically programmable erasable memory device.

Claim 16

A method of forming an improved electrically erasable programmable read only memory device comprising the steps of: providing semiconductor substrate having a dopant of a first conductivity type; forming a first oxide region on the substrate; removing the first oxide forming a depression in the substrate surface; forming a lightly doped source region in the substrate below said depression region; forming a tunnel oxide layer on the substrate surface that fully overlies said lightly doped source; forming a floating gate on the tunnel oxide layer; forming a gate insulation layer on the floating gate; forming a control gate over the floating gate; forming spaced source and drain regions in the substrate separated by a channel region, with the source adjacent to the lightly doped source region, with the lightly doped source region adjacent to the channel region, and the channel region adjacent to the drain; forming a dielectric layer over the control gate and substrate; forming electrical contacts and metallurgy lines with passivation; and connecting the source, drain and control gate to form an electrically programmable erasable memory device.