US5422857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory unit having overlapping addresses
Assignee: Panasonic Holdings Corp
•
Filing: 1994-04-29
•
Granted: 1995-06-06
•
Expires: 2014-04-29
Abstract
Abstract A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines. A plurality of decoders connected to the write word lines decode a write address signal into output signals, respectively, which are fed to the write word lines.
Inventors
- 👤 Kazuki Ninomiya
- 👤 Tomoharu Kawada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:21
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
255 words
A memory unit responsive to an address signal representing a plurality of addresses comprising: a memory cell to which first and second addresses are previously assigned; a first decoder having a first address assignment for states of the address signal, said first decoder directly connected to an address line providing said address signal thereto and connected to the memory cell for decoding a first state of the address signal representing the first address into a first selection signal, and for outputting the first selection signal to access the memory cell; a second decoder having a second address assignment for said states of the address signal, said second address assignment being different from said first address assignment so that said first and second decoders respectively enable access to a specific memory cell in response to two respectively different states of the address signal, said second decoder directly connected to said address line providing said address signal in common thereto and to said first decoder, said second decoder further connected to the memory cell for decoding a second state of the address signal representing the second address into a second selection signal, and for outputting the second selection signal to said memory cell; a common bit line; and means for accessing said memory cell in response to each of the first selection signal and the second selection signal for enabling transmission of data between the memory cell and the common bit line in response to each of said first and second different states of said address signal.
Claim 2
Dependent Claim
255 words
A memory unit responsive to an address signal representing a plurality of addresses comprising: a memory cell to which first and second addresses are previously assigned; a first decoder having a first address assignment for states of the address signal, said first decoder directly connected to an address line providing said address signal thereto and connected to the memory cell for decoding a first state of the address signal representing the first address into a first selection signal, and for outputting the first selection signal to access the memory cell; a second decoder having a second address assignment for said states of the address signal, said second address assignment being different from said first address assignment so that said first and second decoders respectively enable access to a specific memory cell in response to two respectively different states of the address signal, said second decoder directly connected to said address line providing said address signal in common thereto and to said first decoder, said second decoder further connected to the memory cell for decoding a second state of the address signal representing the second address into a second selection signal, and for outputting the second selection signal to said memory cell; a common bit line; and means for accessing said memory cell in response to each of the first selection signal and the second selection signal for enabling transmission of data between the memory cell and the common bit line in response to each of said first and second different states of said address signal.
Claim 3
Dependent Claim
212 words
A memory unit responsive to an address signal, comprising: a memory cell to which first and second addresses are previously assigned; a first decoder having a first address assignment and connected to the memory cell for decoding a first state of the address signal representing the first address into a first selection signal, and for outputting the first selection signal to the memory cell; a second decoder having a second address assignment and connected to the memory cell for decoding a second state of the address signal representing the second address into a second selection signal, and for outputting the second selection signal to the memory cell, the second address assignment being different from the first address assignment; and a common bit line connected to the memory cell; wherein the memory cell comprises a memory element for storing data, first means connected to the first decoder, the memory element, and the common bit line for connecting the memory element and the common bit line to transmit data therebetween in response to the first selection signal, and second means connected to the second decoder, the memory element, and the common bit line for connecting the memory element and the common bit line to transmit data therebetween in response to the second selection signal.
Claim 4
Dependent Claim
212 words
A memory unit responsive to an address signal, comprising: a memory cell to which first and second addresses are previously assigned; a first decoder having a first address assignment and connected to the memory cell for decoding a first state of the address signal representing the first address into a first selection signal, and for outputting the first selection signal to the memory cell; a second decoder having a second address assignment and connected to the memory cell for decoding a second state of the address signal representing the second address into a second selection signal, and for outputting the second selection signal to the memory cell, the second address assignment being different from the first address assignment; and a common bit line connected to the memory cell; wherein the memory cell comprises a memory element for storing data, first means connected to the first decoder, the memory element, and the common bit line for connecting the memory element and the common bit line to transmit data therebetween in response to the first selection signal, and second means connected to the second decoder, the memory element, and the common bit line for connecting the memory element and the common bit line to transmit data therebetween in response to the second selection signal.
Claim 5
Dependent Claim
57 words
A memory unit as recited in claim 2, wherein said first and second addresses are different, and said first and second means operate for connecting the memory element and the common bit line to transmit data therebetween in response to said first and second states of the address signal representing said first and second different addresses, respectively.
Claim 6
Dependent Claim
190 words
A memory unit as recited in claim 2, wherein said first and second means operate for connecting the memory element and the common bit line to transmit data to the memory element from the common bit line for storage therein in response to said first and second states of the address signal representing said first and second addresses, and further comprising: a further common bit line connected to the memory cell; wherein the memory cell further comprises: third means connected to the first decoder, the memory element, and the further common bit line for connecting the memory element and the further common bit line to transmit data from the memory element to the further common bit line in response to the first selection signal corresponding to said first state of the address signal; and fourth means connected to the second decoder, the memory element, and the further common bit line for connecting the memory element and the further common bit line to transmit data from the memory element to the further common bit line in response to the second selection signal corresponding to said second state of the address signal.
Claim 7
Dependent Claim
66 words
A memory unit as recited in claim 4, wherein said first and second addresses are different, said third and fourth means operating for connecting the memory element and the further common bit line to transmit data from the memory element to the further common bit line in response to said first and second states of the address signal representing said first and second different addresses, respectively.
References Cited (Backward Citations)
US4667310A
Cited
JPS60236188A
Cited
US4791607A
Cited
JPS6276092A
Cited
US4775942A
Cited
US4768172A
Cited
US4833648A
Cited
US5023844A
Cited
WO1992008230A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-05 | 1998-12-05 | 1999-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-05 | 2002-12-05 | 2003-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-05 | 2006-12-05 | 2007-06-06 | $7700.00 | Window Closed / Lapsed |