US5422591A
Expired / Lapsed
US
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Output driver circuit with body bias control for multiple power supply operation
Assignee: STMicroelectronics lnc USA
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Filing: 1994-01-03
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Granted: 1995-06-06
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Expires: 2014-01-03
Abstract
Abstract A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off. A first deselect transistor provides a high voltage at the drain of a load transistor to force it into cutoff. A select transistor is turned off to isolate the pull-up transistor well-tie from the output node, and a second deselect transistor is switched on to connect it to ground. This embodiment isolates the well-tie from the driver output while in tri-state to prevent latch-up initiated by multiple power supply operation.
Inventors
- 👤 Bahador Rastegar
- 👤 William C. Slemmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; H03K19/01; H03K19/017; H03K19/01707; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
90 words
An output driver circuit, comprising: a first transistor having a first input signal applied as an input, and formed in an isolated well substrate and a well-tie being attached to the substrate; a second transistor in series with the first transistor having a second input signal applied as an input, the common node between the transistor connected to an output node; and a control circuit for applying a back-bias to the well-tie, the control circuit connecting the well-tie to a selected voltage as a function of the first input signal.
Claim 2
Dependent Claim
90 words
An output driver circuit, comprising: a first transistor having a first input signal applied as an input, and formed in an isolated well substrate and a well-tie being attached to the substrate; a second transistor in series with the first transistor having a second input signal applied as an input, the common node between the transistor connected to an output node; and a control circuit for applying a back-bias to the well-tie, the control circuit connecting the well-tie to a selected voltage as a function of the first input signal.
Claim 3
Dependent Claim
49 words
The output driver circuit of claim 1, wherein the control circuit connects the well-tie of the first transistor to the driver output node when the first input signal is a logic high signal, and to a low rail voltage when the first input signal is a logic low signal.
Claim 4
Dependent Claim
15 words
The output driver circuit of claim 1, wherein the first and second transistors are N-MOSFETs.
Claim 5
Dependent Claim
73 words
The output driver circuit of claim 3, wherein the control circuit comprises; a third N-MOSFET connected between the driver output and the first transistor well-tie such that the third N-MOSFET acts as an active load on the driver output; a fourth N-MOSFET, controlled by the second input signal, connected between the first transistor well-tie and a low voltage rail, wherein a high second input signal connects the well-tie to the low voltage rail.
Claim 6
Dependent Claim
28 words
An output driver circuit of claim 1, wherein the control circuit connects the well-tie to a selected voltage as a function of the first and second input signals.
Claim 7
Dependent Claim
77 words
The output driver circuit of claim 5, wherein the control circuit connects the well-tie to: the driver output when the first input signal is a logic high signal and the second input signal is a logic low; a low voltage rail when the first input signal is a logic low signal and the second input signal is a logic high; and a low voltage rail when the first and second input signals are both a logic low.
Claim 8
Dependent Claim
143 words
The output driver circuit of claim 6, wherein the first and second transistors are N-MOSFETs, and further comprising, within the control circuit: a third transistor having a gate and drain connected to the driver output node; a fourth transistor connected in series with the third transistor creating a common node between them and having an input of the second input signal; a fifth transistor having an input of the second input signal and being connected between the well-tie and ground; a sixth transistor having a deselect input signal connected between a high voltage source and the common node between the third and fourth transistors; a seventh transistor having a select input signal connected between the node common to the third and fourth transistors and the well-tie; and an eighth transistor having an input of the deselect signal connected between the well-tie and ground.
Claim 9
Dependent Claim
187 words
A three state output driver circuit, comprising: a first transistor having a first input signal applied as an input, and formed in an isolated well substrate and a well-tie being attached to the substrate; a second transistor in series with the first transistor having a second input signal applied as an input, the common node between the first and second transistors connected to an output node; a third transistor having a gate and drain connected to the driver output node; a fourth transistor connected in series with the third transistor creating a common node between them and having an input of the second input signal; a fifth transistor having an input of the second input signal and being connected between the well-tie and ground; a sixth transistor having a deselect input signal connected between a high voltage source and the common node between the third and fourth transistors; a seventh transistor having a select input signal connected between the node common to the third and fourth transistors and the well-tie; and an eighth transistor having an input of the deselect signal connected between the well-tie and ground.
Claim 10
Dependent Claim
187 words
A three state output driver circuit, comprising: a first transistor having a first input signal applied as an input, and formed in an isolated well substrate and a well-tie being attached to the substrate; a second transistor in series with the first transistor having a second input signal applied as an input, the common node between the first and second transistors connected to an output node; a third transistor having a gate and drain connected to the driver output node; a fourth transistor connected in series with the third transistor creating a common node between them and having an input of the second input signal; a fifth transistor having an input of the second input signal and being connected between the well-tie and ground; a sixth transistor having a deselect input signal connected between a high voltage source and the common node between the third and fourth transistors; a seventh transistor having a select input signal connected between the node common to the third and fourth transistors and the well-tie; and an eighth transistor having an input of the deselect signal connected between the well-tie and ground.
Claim 11
Dependent Claim
15 words
A three state output driver circuit according to claim 8, wherein the transistors are N-MOSFETs.
Claim 12
Independent Claim
92 words
A method for improving performance of a semiconductor output driver including a first transistor having a first input signal applied as an input, a well-tie being attached to the substrate, a second transistor in series with the first transistor the common node between the transistors connected to an output node, the method comprising the steps of: sensing the input signal; switching the well-tie to connect it to the driver output node when the input signal is high; and switching the well-tie to connect it to ground when the input signal is low.
Claim 13
Independent Claim
92 words
A method for improving performance of a semiconductor output driver including a first transistor having a first input signal applied as an input, a well-tie being attached to the substrate, a second transistor in series with the first transistor the common node between the transistors connected to an output node, the method comprising the steps of: sensing the input signal; switching the well-tie to connect it to the driver output node when the input signal is high; and switching the well-tie to connect it to ground when the input signal is low.
Claim 14
Dependent Claim
45 words
The method for improving performance of a semiconductor output driver of claim 10, wherein the output driver is capable of a three state operation, further comprising the step of switching the well-tie connection to ground when the output driver is placed in a tri-state mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-05 | 1998-12-05 | 1999-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-05 | 2002-12-05 | 2003-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-05 | 2006-12-05 | 2007-06-06 | $7700.00 | Window Closed / Lapsed |