Patent US5418924A successfully refreshed from Google Patents.
US5418924A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory controller with programmable timing
Assignee: Juniper Networks Inc
•
Filing: 1992-08-31
•
Granted: 1995-05-23
•
Expires: 2012-08-31
Abstract
Abstract A memory controller for controlling access to a memory includes a circuit for generating memory signals, including address and control signals, for accessing a memory in response to a physical address, and a circuit for programming the timing of the memory signals in response to predetermined timing control information which defines the timing requirements of the memory. The circuit for programming the timing of the memory preferably includes a register for storing timing control bits and selectors responsive to the timing control bits for selecting timing control parameters from a group of predetermined timing control parameters. The circuit for programming the timing preferably further includes a circuit responsive to each timing control parameter and to a selected memory signal for generating a timing control signal. The timing control signal controls the timing of one of the memory signals. The timing parameters can specify the duration of a memory signal or the time delay between a predefined event in one memory signal and a predefined event in another memory signal. The programmable feature permits the memory controller to be utilized with memories having different timing requirements.
Inventors
- 👤 Scott A. Dresser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/00; G11C7/22; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
130 words
A memory controller for controlling access to a memory, comprising: means for generating memory signals including address and control signals for accessing said memory in response to a physical address, each of said memory signals having at least one timing characteristic; and means for programming the timing characteristic of at least one of said memory signals, said means for programming comprising a control register for storing at least one timing control bit and at least one selector responsive to said timing control bit for selecting a timing parameter from a plurality of predetermined timing parameters, and means responsive to the selected timing parameter and to a selected memory signal for generating a timing control signal, said timing control signal controlling the timing characteristic of said one of said memory signals.
Claim 2
Dependent Claim
130 words
A memory controller for controlling access to a memory, comprising: means for generating memory signals including address and control signals for accessing said memory in response to a physical address, each of said memory signals having at least one timing characteristic; and means for programming the timing characteristic of at least one of said memory signals, said means for programming comprising a control register for storing at least one timing control bit and at least one selector responsive to said timing control bit for selecting a timing parameter from a plurality of predetermined timing parameters, and means responsive to the selected timing parameter and to a selected memory signal for generating a timing control signal, said timing control signal controlling the timing characteristic of said one of said memory signals.
Claim 3
Dependent Claim
65 words
A memory controller as defined in claim 1 wherein said means for generating a timing control signal comprises means for determining an elapsed time after a predefined event in said selected memory signal and means for generating said timing control signal when the elapsed time after said predefined event in said selected memory signal is equal to a value specified by said selected timing parameter.
Claim 4
Dependent Claim
26 words
A memory controller as defined in claim 1 wherein said address and control signals include a row address strobe, a column address strobe and address signals.
Claim 5
Dependent Claim
19 words
A memory controller as defined in claim 1 wherein said timing parameter specifies a predetermined number of clock cycles.
Claim 6
Dependent Claim
54 words
A memory controller as defined in claim 1 wherein said means for generating a timing control signal comprises means for determining a duration of said selected memory and means for generating said timing control signal when the duration of said selected memory signal is equal to a value specified by said selected timing parameter.
Claim 7
Dependent Claim
50 words
A memory controller as defined in claim 1 wherein one of said memory signals comprises a column address strobe signal, wherein said timing characteristic comprises an active time of said column address strobe signal and wherein said means for programming establishes the active time of said column address strobe signal.
Claim 8
Independent Claim
120 words
A method for controlling access to a memory comprising the steps of: generating memory signals including address and control signals for accessing said memory in response to a physical address, each of said memory signal having at least one timing characteristic; and programming the timing characteristic of at least one of said memory signals, comprising the steps of storing at least one timing control bit in a control register, selecting a timing parameter from a plurality of predetermined timing parameters in response to said timing control bit, and generating a timing control signal in response to the selected timing parameter and to selected memory signal, the timing control signal controlling the timing characteristic of said one of said memory signals.
Claim 9
Independent Claim
120 words
A method for controlling access to a memory comprising the steps of: generating memory signals including address and control signals for accessing said memory in response to a physical address, each of said memory signal having at least one timing characteristic; and programming the timing characteristic of at least one of said memory signals, comprising the steps of storing at least one timing control bit in a control register, selecting a timing parameter from a plurality of predetermined timing parameters in response to said timing control bit, and generating a timing control signal in response to the selected timing parameter and to selected memory signal, the timing control signal controlling the timing characteristic of said one of said memory signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-22 | 1998-11-21 | 1999-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-22 | 2002-11-21 | 2003-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-22 | 2006-11-21 | 2007-05-23 | $7700.00 | Window Closed / Lapsed |