Patent US5416739A successfully refreshed from Google Patents.
US5416739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache control apparatus and method with pipelined, burst read
Assignee: VTech Computers Ltd
•
Filing: 1994-03-17
•
Granted: 1995-05-16
•
Expires: 2014-03-17
Abstract
Abstract A cache memory controller capable of servicing pipelined multi-word read memory requests issued by a processor wherein requested data if found to be within a cache memory is bursted to the processor and wherein the servicing of a second pipelined multi-word read memory request issued by the processor overlaps in time with the servicing of a first pipelined multi-word read memory request.
Inventors
- 👤 Kenneth K. F. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0877; G06F12/0879
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
176 words
A cache memory controller capable of servicing multiple, pipelined multi-word read memory requests issued by a processor to a cache memory containing data, the cache memory controller comprising: means for detecting a first pipelined multi-word read memory request issued by the processor; means for initiating a servicing of the first pipelined multi-word read memory request; means for determining whether data within the cache memory corresponds to the first pipelined multi-word read memory request; means for completing the servicing the first pipelined multi-word read memory request; means for detecting a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request; means for initiating the servicing of the second pipelined multi-word read memory request prior to completing the servicing of the first pipelined multi-word read memory request; and means for completing the servicing the second pipelined multi-word read memory request; whereby the servicing of the second pipelined multi-word read memory request overlaps in time with the servicing of the first pipelined multi-word read memory request.
Claim 2
Dependent Claim
176 words
A cache memory controller capable of servicing multiple, pipelined multi-word read memory requests issued by a processor to a cache memory containing data, the cache memory controller comprising: means for detecting a first pipelined multi-word read memory request issued by the processor; means for initiating a servicing of the first pipelined multi-word read memory request; means for determining whether data within the cache memory corresponds to the first pipelined multi-word read memory request; means for completing the servicing the first pipelined multi-word read memory request; means for detecting a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request; means for initiating the servicing of the second pipelined multi-word read memory request prior to completing the servicing of the first pipelined multi-word read memory request; and means for completing the servicing the second pipelined multi-word read memory request; whereby the servicing of the second pipelined multi-word read memory request overlaps in time with the servicing of the first pipelined multi-word read memory request.
Claim 3
Dependent Claim
72 words
The invention according to claim 1 wherein the means for detecting a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request further includes means for indicating to the processor that the cache memory controller is capable of accepting the second pipelined multi-word read memory access prior to completing the servicing of the first pipelined multi-word read memory access.
Claim 4
Independent Claim
160 words
A method of servicing multiple, pipelined multi-word read memory requests issued by a processor to a cache memory containing data, the method comprising the steps of: detecting a first pipelined multi-word read memory request issued by the processor; initiating a servicing of the first pipelined multi-word read memory request; determining whether data within the cache memory corresponds to the first pipelined multi-word read memory request; completing the servicing the first pipelined multi-word read memory request; sensing a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request; beginning the servicing of the second pipelined multi-word read memory request prior to completing the servicing of the first pipelined multi-word read memory request; finishing the servicing of the second pipelined multi-word read memory request; whereby the servicing of the second pipelined multi-word read memory request overlaps in time with the servicing of the first pipelined multi-word read memory request.
Claim 5
Independent Claim
160 words
A method of servicing multiple, pipelined multi-word read memory requests issued by a processor to a cache memory containing data, the method comprising the steps of: detecting a first pipelined multi-word read memory request issued by the processor; initiating a servicing of the first pipelined multi-word read memory request; determining whether data within the cache memory corresponds to the first pipelined multi-word read memory request; completing the servicing the first pipelined multi-word read memory request; sensing a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request; beginning the servicing of the second pipelined multi-word read memory request prior to completing the servicing of the first pipelined multi-word read memory request; finishing the servicing of the second pipelined multi-word read memory request; whereby the servicing of the second pipelined multi-word read memory request overlaps in time with the servicing of the first pipelined multi-word read memory request.
Claim 6
Dependent Claim
73 words
The method according to claim 3 wherein the step of detecting a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request further includes the substep of: indicating to the processor that the cache memory controller is capable of accepting the second pipelined multi-word read memory access prior to completing the servicing of the first pipelined multi-word read memory access.
References Cited (Backward Citations)
US5177706A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-15 | 1998-11-14 | 1999-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-15 | 2002-11-14 | 2003-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-15 | 2006-11-14 | 2007-05-16 | $7700.00 | Window Closed / Lapsed |