Non-volatile random access memory with ferroelectric capacitor

Claim 1

A non-volatile random access memory including a plurality of memory cells, each memory cell comprising a pair of metal oxide semiconductor transistors, said transistors being connected to each other by a common impurity diffusion region, and a capacitor having a ferroelectric film acting as a capacitor dielectric layer, a first electrode of said capacitor being connected to said common impurity diffusion region and a second electrode; and in which one of said pair of metal oxide semiconductor transistors is connected to a bit line and a word line; and electric potentials of said second electrode of the capacitor and an impurity diffusion region provided at the opposite side to said common impurity diffusion region with respect to another of the pair of metal oxide semiconductor transistors are fixed at all times to an intermediate voltage between those available for representing data "1" and "0" and said another of the pair of metal oxide semiconductor transistors is non-conducting when writing or reading data to or from the non-volatile random access memory.