Asynchronous static random access memory device for propagating read-out data bit through single bit line

Claim 1

An asynchronous static random access memory device fabricated on a semiconductor chip, comprising: a) a plurality of first word lines selectively energized in a read-out operation; b) a plurality of second word lines selectively energized in a write-in operation; c) a plurality of first bit lines; d) a plurality of second bit lines respectively paired with said plurality of first bit lines for forming a plurality of bit line pairs; e) a plurality of third bit lines respectively associated with said plurality of bit line pairs for forming a plurality of bit line sets; f) a charging circuit coupled between a first source of voltage level and said plurality of bit line sets for supplying current to said plurality of bit line sets; and g) a plurality of memory cells selectively associated with said plurality of first word lines, said plurality of second word lines and said plurality of bit line sets for said read-out operation and said write-in operation, each of said plurality of memory cells comprising: g-1) a memory circuit having a resistor, a first memory node and a first switching transistor coupled between a first power voltage line and a second power voltage line different in potential level and a series of a second resistor, a second memory node and a second switching transistor coupled between said first power voltage line and said second power voltage line, said first memory node and said second memory node being respectively connected to a gate electrode of said second switching transistor and a gate electrode of said first switching transistor for storing a potential difference indicative of a data bit, g-2) a pair of first switching transistors coupled between said first and second memory nodes and said bit line pair, and gated by one of said plurality of second word lines, g-3) a converting circuit responsive to a voltage level at one of said first and second memory nodes for changing a voltage level on one of said plurality of third bit lines, g-4) a second switching transistor coupled between said one of said plurality of third bit lines and said converting circuit, and gated by one of said plurality of first word lines for enabling said converting circuit to change said voltage level on said one of said plurality of third bit lines, and g-5) a capacitive element coupled with the other of said first and second memory nodes for canceling a parasitic capacitance due to said converting circuit.