Non-volatile random access memory having a high load device

Claim 2

A non-volatile random access memory including a plurality of unit cells, each cell comprising: a transistor composed of source and drain regions and a gate electrode, a ferroelectric capacitor having an accumulating electrode, a ferroelectric film and a cell plate wherein the accumulating electrode is connected to either of the source and drain regions, and a high load device connected to both of the accumulating electrode of the ferroelectric capacitor and the source or drain region connected to the ferroelectric capacitor, wherein the high load device provided in the cell is used with an adjacent cell in common.

Claim 3

A non-volatile random access memory including a plurality of trait cells, each cell comprising: a transistor composed of source and drain regions and a gate electrode, a ferroelectric capacitor having an accumulating electrode, a ferroelectric film and a cell plate wherein the accumulating electrode is connected to either of the source and drain regions, wherein the ferroelectric capacitor covers a portion of the transistor and the high load device, and a high load device connected to both of the accumulating electrode of the ferroelectric capacitor and the source or drain region connected to the ferroelectric capacitor.

Claim 4

A non-volatile random access memory including a plurality of trait cells, each cell comprising: a transistor composed of source and drain regions and a gate electrode, a ferroelectric capacitor having an accumulating electrode, a ferroelectric film and a cell plate wherein the accumulating electrode is connected to either of the source and drain regions, wherein the ferroelectric capacitor covers a portion of the transistor and the high load device, and a high load device connected to both of the accumulating electrode of the ferroelectric capacitor and the source or drain region connected to the ferroelectric capacitor.

Claim 5

A non-volatile random access memory including a plurality of unit cells, each cell comprising: a transistor composed of source and drain regions and a gate electrode, a ferroelectric capacitor having an accumulating electrode, a ferroelectric film and a cell plate wherein the accumulating electrode is connected to either of the source and drain regions, and a high load transistor connected to both of the accumulating electrode of the ferroelectric capacitor and the source or drain region connected to the ferroelectric capacitor, wherein the high load transistor comprises source and drain regions and a gate electrode, one of the source and drain regions being conductively coupled to the gate electrode of the high load transistor, the other of the source and drain regions in the high load transistor being conductively coupled to one of the source and drain regions of the transistor connected to the accumulating electrode of the ferroelectric capacitor.

Claim 6

A non-volatile random access memory including a plurality of unit cells, each cell comprising: a transistor composed of source and drain regions and a gate electrode, a ferroelectric capacitor having an accumulating electrode, a ferroelectric film and a cell plate wherein the accumulating electrode is connected to either of the source and drain regions, and a high load transistor connected to both of the accumulating electrode of the ferroelectric capacitor and the source or drain region connected to the ferroelectric capacitor, wherein the high load transistor comprises source and drain regions and a gate electrode, one of the source and drain regions being conductively coupled to the gate electrode of the high load transistor, the other of the source and drain regions in the high load transistor being conductively coupled to one of the source and drain regions of the transistor connected to the accumulating electrode of the ferroelectric capacitor.

Claim 7

The non-volatile memory of claim 3, wherein each of the plurality of cells is connected respectively to a plurality of word lines and bit lines, the gate of the high load transistor in each cell is connected to a common word line, and for each cell the source or drain region coupled to the gate electrode of the high load transistor are conductively coupled wherein gate electrode is shared between cells.