Semiconductor device using boosted signal

Claim 2

A semiconductor device carrying out a predetermined operation in response to a timing at which a third control signal provided in response to first and second control signals changes from a first voltage level to a boosted second voltage level, comprising: output means for providing said second control signal delayed from said first control signal; and control signal output means for providing said third control signal rising from said first voltage level to said second voltage level, wherein said third control signal is pulled up to a third voltage level which is intermediate between said first voltage level and said second voltage level in response to said first control signal, and then pulled up to said second voltage level in response to said second control signal.

Claim 3

The semiconductor device as recited in claim 1, wherein said third voltage level is a power supply voltage level externally supplied to said semiconductor device, said second voltage level is a boosted voltage level obtained by boosting said power supply voltage, and said first voltage level is a ground potential.

Claim 4

The semiconductor device as recited in claim 1, wherein said control signal output means includes first selecting means for selectively providing an output signal at said first voltage level or an output signal at said third voltage level in response to said first control signal, and second selecting means for selectively providing an output signal at said second voltage level or an output signal selected by said first selecting means in response to said second control signal.

Claim 5

The semiconductor device as recited in claim 3, wherein said second control signal includes a signal at said third voltage level, and said second selecting means includes level converting means for converting said second control signal at said third voltage level into a fourth control signal at said second voltage level for output, and third selecting means for selectively providing an output signal at said second voltage level or an output signal selected by said first selecting means in response to said fourth control signal.

Claim 6

The semiconductor device as recited in claim 4, wherein said first selecting means includes a first PMOS transistor connected to a voltage of said third voltage level and having a gate receiving said first control signal, and a first NMOS transistor connected to a voltage of said first voltage level and said first PMOS transistor and having a gate receiving said first control signal, said second control signal includes two complementary signals complementary to each other, said level converting means includes a second PMOS transistor connected to a voltage of said second voltage level, a second NMOS transistor connected to a voltage of said first voltage level and said second PMOS transistor and having a gate receiving one of said complementary signals, a third PMOS transistor connected to a voltage of said second voltage level and having a gate receiving a signal at a connection portion of said second PMOS transistor and said second NMOS transistor, and a third NMOS transistor connected to a voltage of said first voltage level and said third PMOS transistor and having a gate receiving the other of said complementary signals, said second PMOS transistor has a gate receiving a signal at a connection portion of said third PMOS transistor and said third NMOS transistor, said third selecting means includes a fourth PMOS transistor connected to a voltage of said second voltage level and having a gate receiving a signal at a connection portion of said third PMOS transistor and said third NMOS transistor, and a fourth NMOS transistor connected to said fourth PMOS transistor and a connection portion of said first PMOS transistor and said first NMOS transistor, and having a gate receiving a signal at a connection portion of said third PMOS transistor and said third NMOS transistor.

Claim 7

The semiconductor device as recited in claim 3, wherein said first and second selecting means are provided in plural, respectively, and respective connection portions of said first selecting means and said second selecting means are connected together.

Claim 8

The semiconductor device as recited in claim 1, wherein said control signal output means includes first selecting means responsive to said second control signal for selectively providing an output signal at said first voltage level or an output signal at said second voltage level, and second selecting means responsive to said first control signal for selectively providing an output signal at said third voltage level or an output signal selected by said first selecting means.

Claim 9

The semiconductor device as recited in claim 7, wherein said second control signal includes a signal at said third voltage level, said first selecting means includes level converting means for providing a fourth control signal obtained by conversion of said third voltage level of said second control signal into said second voltage level, and third selecting means responsive to said fourth control signal for selectively providing an output signal at said first voltage level or an output signal at said second voltage level.

Claim 10

The semiconductor device as recited in claim 8, wherein said second control signal includes two complementary signals complementary to each other, said level converting means includes a first PMOS transistor connected to a voltage of said second voltage level, a first NMOS transistor connected to a voltage of said first voltage level and said first PMOS transistor and having a gate receiving said one complementary signal, a second PMOS transistor connected to a voltage of said second voltage level and having a gate receiving a signal at a connection portion of said first PMOS transistor and said first NMOS transistor, and a second NMOS transistor connected to a voltage of said first voltage level and said second PMOS transistor and having a gate receiving said the other complementary signal, said first PMOS transistor has a gate receiving a signal at a connection portion of said second PMOS transistor and said second NMOS transistor, said third selecting means includes a third PMOS transistor connected to a voltage of said second voltage level and having a gate receiving a signal at a connection portion of said second PMOS transistor and said second NMOS transistor, and a third NMOS transistor connected to a voltage of said first voltage level and said third PMOS transistor and having a gate receiving said one complementary signal, said second selecting means includes inverting means for inverting said first control signal, and a fourth NMOS transistor connected between a voltage of said third voltage level and a connection portion of said third PMOS transistor and said third NMOS transistor and having a gate receiving an output signal of said inverting means.

Claim 11

The semiconductor device as recited in claim 1, further comprising: first and second storage means for storing information; amplifying means for amplifying an information signal output from said first or second storage means; first connecting means for connecting said first storage means and said amplifying means when a voltage level of said third control signal is said third voltage level, and for disconnecting said first storage means and said amplifying means when the voltage level of said third control signal is said first voltage level, and second connecting means for connecting said second storage means and said amplifying means when the voltage level of said third control signal is said third voltage level, and disconnecting said second storage means and said amplifying means when the voltage level of said third control signal is said first voltage level, said control signal output means outputs two first control signals corresponding to said first and second connecting means, and turns on one of said first and second connecting means when said semiconductor device is in an operative state.

Claim 12

The semiconductor device as recited in claim 10, wherein said output means includes first output means responsive to a define signal defining an operative state of said semiconductor device for providing said first control signal, delay means for delaying said define signal and providing a delay signal, second output means responsive to a select signal selecting said storage means for providing an instruction signal instructing selection or non-selection for each storage means when said delay signal is in an active state, and third output means responsive to said instruction signal for providing said second control signal.

Claim 13

The semiconductor device as recited in claim 11, wherein said semiconductor device is a dynamic random access memory, said define signal is a row address strobe signal, and said select signal is a row address signal.

Claim 14

The semiconductor device as recited in claim 11, wherein said semiconductor device is a dynamic random access memory, said define signal is an externally applied define signal, said first output means further includes self-refresh operation detecting means for detecting self-refresh operation according to said define signal, and clock signal generating means responsive to a self-refresh operation sense signal provided from said self-refresh operation detecting means for providing a clock signal of a predetermined cycle.

Claim 15

The semiconductor device as recited in claim 13, wherein said define signal is an externally applied row address strobe signal and column address strobe signal, said self-refresh operation detecting means detects self-refresh operation in response to a row address strobe signal attaining an active state after said column address strobe signal attaining an active state.

Claim 16

The semiconductor device as recited in claim 1, further comprising a memory cell array including a plurality of memory cells disposed in row and column directions, a plurality of bit lines each connected to a corresponding one of said memory cells, and a plurality of word lines each connected to a corresponding one of said memory cells, wherein said control signal output means includes means for providing said third control signal as a control signal for activating said word line.

Claim 17

A semiconductor device, comprising: first and second storage means for storing information; amplifying means for amplifying an information signal output from said first or second storage means; connecting means responsive to a control signal for selectively connecting said amplifying means and said first or second storage means; and control signal output means for pulling up said control signal from a first voltage level to a boosted second voltage level, wherein said control signal is pulled up from said first voltage level to a third voltage level which is intermediate between said first voltage level and said second voltage level, and then pulled up to said second voltage level from said third voltage level.

Claim 18

A semiconductor device, comprising: first and second storage means for storing information; amplifying means for amplifying an information signal output from said first or second storage means; connecting means responsive to a control signal for selectively connecting said amplifying means and said first or second storage means; and control signal output means for pulling up said control signal from a first voltage level to a boosted second voltage level, wherein said control signal is pulled up from said first voltage level to a third voltage level which is intermediate between said first voltage level and said second voltage level, and then pulled up to said second voltage level from said third voltage level.