Image output control apparatus

Claim 2

An image output control apparatus comprising: a bus to which a display unit is connected and through which passes the data corresponding to images to be displayed on the screen of said display unit; a video data generating block for generating video data which is digitized and which corresponds to a video image to be displayed on said screen; a digital data generating block for generating digital data representing a digitized character and graphic image to be displayed on said screen; and a video priority signal generating circuit for outputting a video priority signal designating that said video data be preferentially output onto said bus; said video data generating block further comprising: an area generating circuit for outputting an area designation signal designating the area in which to display said video image on said screen; a digital data inhibit signal generating circuit for generating a digital data inhibit signal in response to the presence of both said area designation signal and said video priority signal; and a first inhibit circuit for inhibiting the output of said video data onto said bus in accordance with a second inhibit signal; said digital data generating block further comprising: a transparency discriminating circuit for checking to see if said digital data indicates any transparent pixel and, upon detecting a transparent pixel, for generating a transparency signal; an inhibit signal generating circuit for generating a first inhibit signal and said second inhibit signal in accordance with said digital data inhibit signal and said transparency signal; and a second inhibit circuit for inhibiting the output of said digital data onto said bus in accordance with said first inhibit signal.

Claim 3

An image output control apparatus according to claim 1, wherein said inhibit signal generating circuit makes said first inhibit signal active when at least either of said transparency signal and said digital data inhibit signal is active, and makes said second inhibit signal active when said first inhibit signal is inactive.

Claim 4

An image output control apparatus according to claim 2, wherein said video data generating block outputs the video data stored in a first memory onto said bus in accordance with a timing signal when said second inhibit signal is inactive; and wherein said digital data generating block outputs the digital data stored in a second memory onto said bus in accordance with said timing signal when said first inhibit signal is inactive.

Claim 5

An image output control apparatus according to claim 3, wherein: said digital data inhibit signal generating circuit further comprises an AND gate for AND'ing said video priority signal and said area designation signal and outputting the result therefrom; said first inhibit circuit further comprises a bus buffer which is interposingly provided between said :first memory and said bus and which is placed in a conductive state when said second inhibit signal is inactive; said second inhibit circuit further comprises a bus buffer which is interposingly provided between said second memory and said bus and which is placed in a conductive state when said first inhibit signal is inactive; and said inhibit signal generating circuit further comprises an OR gate for OR'ing said transparency signal and said digital data inhibit signal and outputting the result therefrom as said first inhibit signal, and an inverting gate for inverting said first inhibit signal to generate said second inhibit signal.

Claim 6

An image output control apparatus according to claim 1, wherein said area generating circuit further comprises: an "x" enable signal generating circuit for generating a horizontal enable signal; a "y" enable signal generating circuit for generating a vertical enable signal; and an AND gate for AND'ing the output of said "x" enable signal generating circuit and that of said "y" enable signal generating circuit and outputting the result therefrom as said area designation signal.

Claim 7

An image output control apparatus according to claim 5, wherein said "x" enable signal generating circuit further comprises: a first counter for counting clock signals in synchronization with pixels; a first comparator for comparing a parameter indicating a horizontal display start position with the count value of said first counter; a second comparator for comparing a parameter indicating a horizontal display end position with the count value of said first counter; and a flip-flop circuit which is set by a coincidence signal from said first comparator and is reset by a coincidence signal from said second comparator; and wherein said "y" enable signal generating circuit further comprises: a second counter for counting clock signals in synchronization with pixels; a third comparator for comparing a parameter indicating a vertical display start position with the count value of said second counter; a fourth comparator for comparing a parameter indicating a vertical display end position with the count value of said second counter; and a flip-flop circuit which is set by a coincidence signal from said third comparator and is reset by a coincidence signal from said fourth comparator.

Claim 8

The image output control apparatus of claim 1, wherein said digital data inhibit signal generating circuit generates said digital data inhibit signal by performing a logical AND between said area designation signal and said video priority signal.

Claim 9

An image output control apparatus comprising: a bus to which a display unit is connected and through which passes the data corresponding to images to be displayed on the screen of said display unit; a plurality of data output circuits each containing a video data generating block for generating video data which is digitized and which corresponds to a video image to be displayed on said screen, and a digital data generating block for generating: digital data representing a digitized character and graphic image to be displayed on said screen; a priority discriminating means for determining one of said plurality of data output circuits, said determined data output circuit being allowed to output data onto said bus; and a video priority signal generating circuit which is assigned to each of said data output circuits and which outputs a video priority signal designating that said video data be preferentially output onto said bus; each of said video data generating blocks further comprising: an area generating circuit for outputting an area designation signal designating the area in which to display said video image on said screen; a digital data inhibit signal generating circuit for generating a digital data inhibit signal in response to the presence of both said area designation signal and said video priority signal; and a first inhibit circuit for inhibiting the output of said video data onto said bus in accordance with a second inhibit signal; each of said digital data generating blocks further comprising: a transparency discriminating circuit for checking to see if said digital data indicates any transparent pixel and, upon detecting a transparent pixel, for generating a transparency signal; an inhibit signal generating circuit for generating a first inhibit signal and said second inhibit signal in accordance with said digital data inhibit signal and said transparency signal; and a second inhibit circuit for inhibiting the output of said digital data onto said bus in accordance with said first inhibit signal.

Claim 10

An image output control apparatus comprising: a bus to which a display unit is connected and through which passes the data corresponding to images to be displayed on the screen of said display unit; a plurality of data output circuits each containing a video data generating block for generating video data which is digitized and which corresponds to a video image to be displayed on said screen, and a digital data generating block for generating: digital data representing a digitized character and graphic image to be displayed on said screen; a priority discriminating means for determining one of said plurality of data output circuits, said determined data output circuit being allowed to output data onto said bus; and a video priority signal generating circuit which is assigned to each of said data output circuits and which outputs a video priority signal designating that said video data be preferentially output onto said bus; each of said video data generating blocks further comprising: an area generating circuit for outputting an area designation signal designating the area in which to display said video image on said screen; a digital data inhibit signal generating circuit for generating a digital data inhibit signal in response to the presence of both said area designation signal and said video priority signal; and a first inhibit circuit for inhibiting the output of said video data onto said bus in accordance with a second inhibit signal; each of said digital data generating blocks further comprising: a transparency discriminating circuit for checking to see if said digital data indicates any transparent pixel and, upon detecting a transparent pixel, for generating a transparency signal; an inhibit signal generating circuit for generating a first inhibit signal and said second inhibit signal in accordance with said digital data inhibit signal and said transparency signal; and a second inhibit circuit for inhibiting the output of said digital data onto said bus in accordance with said first inhibit signal.

Claim 11

An image output control apparatus according to claim 8, wherein said priority discriminating means further comprises: a channel area generating circuit which is assigned to each of said data output circuits and which generates a channel area designation signal designating the display area to be handled by the data output circuit assigned thereto; and a channel priority determining circuit for admitting each of said channel area designation signals and outputting a channel enable signal in accordance with the channel area designation signal selected based on a predetermined priority.

Claim 12

An image output control apparatus according to claim 9, wherein said channel area generating circuit further comprises: an "x" enable signal generating circuit for generating a horizontal enable signal; a "y" enable signal generating circuit for generating a vertical enable signal; and an AND gate for AND'ing the output of said "x" enable signal generating circuit and that of said "y" enable signal generating circuit and outputting the result therefrom as said channel area designation signal.

Claim 13

An image output control apparatus according to claim 10, wherein said "x" enable signal generating circuit further comprises: a first counter for counting clock signals in synchronization with pixels; a first comparator for comparing a parameter indicating a horizontal display start position with the count value of said first counter; a second comparator for comparing a parameter indicating a horizontal display end position with the count value of said first counter; and a flip-flop circuit which is set by a coincidence signal from said first comparator and is reset by a coincidence signal from said second comparator; and wherein said "y" enable signal generating circuit further comprises: a second counter for counting clock signals in synchronization with pixels; a third comparator for comparing a parameter indicating a vertical display start position with the count value of said second counter; a fourth comparator for comparing a parameter indicating a vertical display end position with the count value of said second counter; and a flip-flop circuit which is set by a coincidence signal from said third comparator and is reset by a coincidence signal from said fourth comparator.

Claim 14

An image output control apparatus according to claim 9, wherein said inhibit signal generating circuit makes said second inhibit signal active when at least either of said transparency signal and said digital data inhibit signal is active while said channel enable signal is being output; and wherein said digital data inhibit signal generating circuit makes said digital data inhibit signal active when said area designation signal and said video priority signal both become active while said channel enable signal is being output.

Claim 15

An image output control apparatus according to claim 12, wherein said video data generating block outputs the video data stored in a first memory onto said bus in accordance with a timing signal when said second inhibit signal is inactive; and wherein said digital data generating block outputs the digital data stored in a second memory onto said bus in accordance with said timing signal when said first inhibit signal is inactive.

Claim 16

An image output control apparatus according to claim 13, wherein: said digital data inhibit signal generating circuit further comprises an AND gate which is enabled by said channel enable signal for AND'ing said video priority signal and said area designation signal and outputting the result therefrom; said first inhibit circuit further comprises a bus buffer which is interposingly provided between said first memory and said bus and which is placed in a conductive state when said second inhibit signal is inactive; said second inhibit circuit further comprises a bus buffer which is interposingly provided between said second memory and said bus and which is placed in a conductive state when said first inhibit signal is inactive; and said inhibit signal generating circuit further comprises an OR gate for OR'ing said transparency signal and said digital data inhibit signal and outputting the result therefrom as said first inhibit signal, and an inverting gate which is enabled by said channel enable signal for inverting said first inhibit signal to generate said second inhibit signal.

Claim 17

The image output control apparatus of claim 8, wherein said digital data inhibit signal generating circuit generates said digital data inhibit signal by performing a logical AND between said area designation signal and said video priority signal.

Claim 18

An image output control apparatus comprising: first memory means for storing video image data; second memory means for storing digital data; video priority signal means for generating a logical high level signal if the video image data has priority for a pixel to be driven; transparency discriminating means, responsive to said second memory means, for generating a logical high level signal if the digital data stored in said second memory means relating to said pixel is transparent; and control means, responsive to said first memory means and said video priority signal means, for driving said pixel based on video image data relating to said pixel stored in said first memory means if either of said video priority signal means or said transparency discriminating means generates a logical high level signal.

Claim 19

An image output control apparatus comprising: first memory means for storing video image data; second memory means for storing digital data; video priority signal means for generating a logical high level signal if the video image data has priority for a pixel to be driven; transparency discriminating means, responsive to said second memory means, for generating a logical high level signal if the digital data stored in said second memory means relating to said pixel is transparent; and control means, responsive to said first memory means and said video priority signal means, for driving said pixel based on video image data relating to said pixel stored in said first memory means if either of said video priority signal means or said transparency discriminating means generates a logical high level signal.