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Patent US5410262A successfully refreshed from Google Patents.
US5410262A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data output buffer of a semiconductor integrated circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-06-08
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Granted: 1995-04-25
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Expires: 2014-06-08
Abstract
Abstract A data output buffer of a semiconductor integrated circuit is operable in response to data input to data lines and comprises a first pull-down control circuit which generates a first pull-down signal in response to the data input to the data lines. A second pull-down control circuit generates a second pull-down signal in response to the data input to the data lines, the second pull-down signal being generated at a predetermined time after the first pull-down signal is generated and causing the first pull down signal to be deactivated. A first pull-down transistor shares an output node with a pull-up transistor and is responsive to the first pull-down signal to pull-down a predetermined amount of voltage at the output node. A second pull-down transistor is responsive to the second pull down signal for pulling down a residual amount of voltage at the output node.
Inventors
- 👤 Kyung-Woo Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:38
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/22
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
157 words
A data output buffer of a semiconductor integrated circuit operable in response to data input to data lines and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to said data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a pull-up transistor; a first pull-down transistor sharing an output node with said pull-up transistor and being responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at said output node; and a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node.
Claim 2
Dependent Claim
157 words
A data output buffer of a semiconductor integrated circuit operable in response to data input to data lines and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to said data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a pull-up transistor; a first pull-down transistor sharing an output node with said pull-up transistor and being responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at said output node; and a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node.
Claim 3
Dependent Claim
30 words
A data output buffer as claimed in claim 1, wherein said second pull-down control circuit comprises a delay circuit having at least three inverters connected in series to one another.
Claim 4
Dependent Claim
18 words
A data output buffer as claimed in claim 2, wherein said delay circuit further comprises a nand gate.
Claim 5
Dependent Claim
23 words
A data output buffer as claimed in claim 3, wherein said first pull-down control circuit comprises said nand gate and a nor gate.
Claim 6
Dependent Claim
26 words
A data output buffer as claimed in claim 1, further comprising clock input means for receiving an input clock signal to drive said data output buffer.
Claim 7
Dependent Claim
23 words
A data output buffer as claimed in claim 1, further comprising a resistance disposed between said second pull-down transistor and said ground line.
Claim 8
Dependent Claim
22 words
A data output buffer as claimed in claim 1, further comprising a capacitor connected between the output node and the ground line.
Claim 9
Dependent Claim
162 words
A data output buffer of a semiconductor integrated circuit connected to a pair of data lines for receiving data read from a memory cell array and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a first pull-down transistor responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at an output node; a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node; and a resistance disposed between said second pull-down transistor and said ground line.
Claim 10
Dependent Claim
162 words
A data output buffer of a semiconductor integrated circuit connected to a pair of data lines for receiving data read from a memory cell array and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a first pull-down transistor responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at an output node; a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node; and a resistance disposed between said second pull-down transistor and said ground line.
Claim 11
Dependent Claim
32 words
A data output buffer as claimed in claim 8, wherein said second pull-down control circuit comprises a delay circuit including a plurality of inverters for delaying generation of said second pull-down signal.
Claim 12
Dependent Claim
23 words
A data output buffer as claimed in claim 9, further comprising a pull-up transistor sharing the output node with said first pull-down transistor.
Claim 13
Dependent Claim
176 words
A data output buffer of a semiconductor integrated circuit connected to a pair of data lines for receiving data read from a memory cell array and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a pull-up transistor; a first pull-down transistor sharing an output node with said first pull-up transistor and being responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at the output node; a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node; and a resistance disposed between said second pull-down transistor and said ground line.
Claim 14
Dependent Claim
176 words
A data output buffer of a semiconductor integrated circuit connected to a pair of data lines for receiving data read from a memory cell array and connected between a power supply line and a ground line, comprising: a first pull-down control circuit for generating a first pull-down signal in response to data input to said data lines; a second pull-down control circuit for generating a second pull-down signal in response to said data input to said data lines, said second pull-down signal being generated at a predetermined time after said first pull-down signal is generated and causing said first pull down signal to be deactivated; a pull-up transistor; a first pull-down transistor sharing an output node with said first pull-up transistor and being responsive to said first pull-down signal for pulling-down a predetermined amount of voltage at the output node; a second pull-down transistor responsive to said second pull down signal for pulling down a residual amount of voltage at the output node; and a resistance disposed between said second pull-down transistor and said ground line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |