US5410194A
Expired / Lapsed
US
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Asynchronous or synchronous load multifunction flip-flop
Assignee: Xilinx Inc
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Filing: 1993-08-11
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Granted: 1995-04-25
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Expires: 2013-08-11
Abstract
Abstract According to the present invention hardware is provided in a user configurable logic integrated circuit chip to allow a user to select multiple storage functions such as D, T, JK, to receive multiple input signals and generate a storage input signal using a function such as OR or MUX, along with parallel load and asynchronous load options. A relatively small hardware area can offer these functions, which are commonly used, and can leave general purpose logic for other more complex functions, thus increasing the amount of logic which a user may implement in a given silicon area.
Inventors
- 👤 Philip M. Freidin
- 👤 Charles R. Erickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K19/17704; H03K19/17736; H03K19/1774; H03K19/1776
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
A flipflop comprising: a D flipflop having at least a data input, a clock input, and an output; means for receiving a plurality of signals; means for processing said plurality of signals according to a user-specified function to generate an intermediate output; means for providing said intermediate output to an input of said D flipflop in which said means for receiving a plurality of signals receives a first signal D1 and a second signal D2; and further comprising: means for receiving a clock enable signal; means for receiving a parallel enable signal; a first multiplexer which receives as input said first signal D1 and a signal Q from said output signal which is controlled by said clock enable signal, and which generates a first multiplexer output signal; a second multiplexer which receives as input said first multiplexer output signal and said second signal D2 and is controlled by said parallel enable signal and generates a second multiplexer output signal which drives said input of said D flipflop.
Claim 2
Dependent Claim
167 words
A flipflop comprising: a D flipflop having at least a data input, a clock input, and an output; means for receiving a plurality of signals; means for processing said plurality of signals according to a user-specified function to generate an intermediate output; means for providing said intermediate output to an input of said D flipflop in which said means for receiving a plurality of signals receives a first signal D1 and a second signal D2; and further comprising: means for receiving a clock enable signal; means for receiving a parallel enable signal; a first multiplexer which receives as input said first signal D1 and a signal Q from said output signal which is controlled by said clock enable signal, and which generates a first multiplexer output signal; a second multiplexer which receives as input said first multiplexer output signal and said second signal D2 and is controlled by said parallel enable signal and generates a second multiplexer output signal which drives said input of said D flipflop.
Claim 3
Dependent Claim
67 words
A flipflop as in claim 1 in which said D flipflop further comprises; a set input and a reset input; and further comprising: means for receiving a second plurality of signals; means for processing said second plurality of signals according to a user specified function to generate a second intermediate output; means for providing said second intermediate output to one of said inputs of said D flipflop.
Claim 4
Dependent Claim
93 words
A flipflop as in claim 2 in which said second plurality of signals comprises: an asynchronous load enable signal, and an asynchronous data signal; and said means for providing said second intermediate output to one of said inputs of said D flip flop comprises: means for providing a high signal to said set input when said asynchronous load enable signal and said asynchronous data signal are high, and means for providing a high signal to said reset input when said asynchronous load enable signal is high and said asynchronous data signal is low.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |