Patent US5408671A successfully refreshed from Google Patents.
US5408671A
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US
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System for controlling shared registers
Assignee: NEC Corp
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Filing: 1992-03-19
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Granted: 1995-04-18
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Expires: 2012-03-19
Abstract
Abstract By using a shared register directory having a bit array corresponding one to one to the processor for each shared register, a shared register control portion of a shared register control system in a multiprocessor system monitors to which processor each of the registers shared between processors is currently allocated or if it is not allocated to any of the processors at all (unoccupied condition), and allocates any arbitrary shared register in response to the request from each processor while allowing access to the allocated share register. A task on the processor, which had been initially using the shared register, can be switched even if another task using the same register is being executed on any other processor, and the throughput of the multiprocessor system using the shared register can be increased.
Inventors
- 👤 Kouji Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:09
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
309 words
A system for controlling registers shared among a plurality of processors in a multiprocessor computer system comprising: a plurality of shared registers each being accessed from said processors, said shared registers being present in a number corresponding to that of said processors; and a shared register control portion having a shared register directory providing bit arrays corresponding one-to-one to said processors for each of said shared registers, wherein said shared register control portion manages allocation of said shared registers to said processors and their unoccupied condition according to a setting and a resetting of each bit of the bit arrays of said shared register directory and allocates any arbitrary shared register in response to a request for allocation of an unoccupied register from each of said processors and wherein said shared register control portion further comprises, control means connected to said processors to receive a request for said shared registers and for controlling changing the bits of said shared register directory; shared bit reset means, shared register selector means and shared bit set means connected between said control means and said shared register directory, said shared bit set means setting bits of said bit arrays of said shared register directory, said shared bit reset means resetting a bit of said bit arrays of said shared register directory corresponding to a shared register whose use is to be discontinued by one of said processors, said shared register selector means selecting one of said shared registers corresponding to said bit array, all the bits of which are reset; and access control means, connected between said processors and said shared registers, for allowing access from one of said processors corresponding to one of the set bits of each bit array of said shared register directory to a shared register corresponding to a shared register corresponding to a bit array including said bit.
Claim 2
Independent Claim
309 words
A system for controlling registers shared among a plurality of processors in a multiprocessor computer system comprising: a plurality of shared registers each being accessed from said processors, said shared registers being present in a number corresponding to that of said processors; and a shared register control portion having a shared register directory providing bit arrays corresponding one-to-one to said processors for each of said shared registers, wherein said shared register control portion manages allocation of said shared registers to said processors and their unoccupied condition according to a setting and a resetting of each bit of the bit arrays of said shared register directory and allocates any arbitrary shared register in response to a request for allocation of an unoccupied register from each of said processors and wherein said shared register control portion further comprises, control means connected to said processors to receive a request for said shared registers and for controlling changing the bits of said shared register directory; shared bit reset means, shared register selector means and shared bit set means connected between said control means and said shared register directory, said shared bit set means setting bits of said bit arrays of said shared register directory, said shared bit reset means resetting a bit of said bit arrays of said shared register directory corresponding to a shared register whose use is to be discontinued by one of said processors, said shared register selector means selecting one of said shared registers corresponding to said bit array, all the bits of which are reset; and access control means, connected between said processors and said shared registers, for allowing access from one of said processors corresponding to one of the set bits of each bit array of said shared register directory to a shared register corresponding to a shared register corresponding to a bit array including said bit.
Claim 3
Dependent Claim
335 words
A multiprocessor Computer system including a plurality of processors, comprising: a plurality of shared registers, equal in number to the plurality of processors, each of said shared registers selectably connected to each of said processors; a shared register controller, connected between said processors and Said shared register, said shared register controller including a shared register directory having a plurality of bit arrays, one bit array corresponding to each of said shared registers, each of said bit arrays including a bit corresponding to each of said processors, a bit set to a first logical value in a bit array indicating that one of said processors, corresponding to said bit, is using the shared register corresponding to said bit array, a bit set to a second logical value indicating that the corresponding processor is not using the shared register corresponding to said bit array, said shared register controller effective to allocate said shared registers to said processors upon a request from said processors by setting and resetting bits in said bit arrays and wherein said shared register controller further comprises, control means receiving requests for said shared registers from said processors; shared bit set means, connected between said control means and said bit arrays, for resetting a bit in said bit arrays corresponding to a processor request for use for one of said shared registers to said first logical value; shared bit reset means, connected between said control means and said bit arrays, for resetting a bit of said bit arrays corresponding to a shared register whose use is to be discontinued by one of said processors, to said second logical value; shared register selector means, connected between said control means and said bit arrays, for determining a bit array all of whose bits are set to said second logical value indicating that the corresponding shared register is not being used by any of said processor; and access control means for selectably connecting said processors to said shared registers according to said bits of said bit arrays.
Claim 4
Dependent Claim
335 words
A multiprocessor Computer system including a plurality of processors, comprising: a plurality of shared registers, equal in number to the plurality of processors, each of said shared registers selectably connected to each of said processors; a shared register controller, connected between said processors and Said shared register, said shared register controller including a shared register directory having a plurality of bit arrays, one bit array corresponding to each of said shared registers, each of said bit arrays including a bit corresponding to each of said processors, a bit set to a first logical value in a bit array indicating that one of said processors, corresponding to said bit, is using the shared register corresponding to said bit array, a bit set to a second logical value indicating that the corresponding processor is not using the shared register corresponding to said bit array, said shared register controller effective to allocate said shared registers to said processors upon a request from said processors by setting and resetting bits in said bit arrays and wherein said shared register controller further comprises, control means receiving requests for said shared registers from said processors; shared bit set means, connected between said control means and said bit arrays, for resetting a bit in said bit arrays corresponding to a processor request for use for one of said shared registers to said first logical value; shared bit reset means, connected between said control means and said bit arrays, for resetting a bit of said bit arrays corresponding to a shared register whose use is to be discontinued by one of said processors, to said second logical value; shared register selector means, connected between said control means and said bit arrays, for determining a bit array all of whose bits are set to said second logical value indicating that the corresponding shared register is not being used by any of said processor; and access control means for selectably connecting said processors to said shared registers according to said bits of said bit arrays.
References Cited (Backward Citations)
US3735360A
Cited
US4110830A
Cited
US4136386A
Cited
US4513367A
Cited
EP0170443A2
Cited
US4885680A
Cited
WO1988007720A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |