Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared

Claim 2

A microcomputer comprising: a bus; a central processing unit coupled to said bus; a watchdog timer coupled to said bus, and generating a watchdog timer processing request when an overflow occurs in said watchdog timer, said watchdog timer being cleared by a watchdog timer clear signal generated by said central processing unit; an interrupt control circuit coupled to said bus, and receiving said watchdog timer processing request and at least one interrupt processing request, said interrupt control circuit including: an interrupt request flag group having a first interrupt request flag set by said watchdog timer processing request and a second interrupt request flag set by said at least one interrupt processing request, a priority level control unit including first and second latches provided in correspondence to said first and second interrupt request flags, respectively, said priority level control unit being coupled directly to an output of said first interrupt request flag, for generating an active interrupt request signal to said central processing unit when the output of at least one of said first and second interrupt request flags is active, said priority level control unit operating to output an active signal to the latch corresponding to the processing request having the highest priority among the processing requests being generated, when the output of at least one of said first and second interrupt request flags is active, said active signal being latched into the corresponding latch in response to an interrupt acknowledge signal generated by said central processing unit after said central processing unit has received said active interrupt request signal, and a vector generation unit coupled to receive an output of each of said first and second latches, for outputting through said bus to said central processing unit, a vector information corresponding to the latch which has latched said active signal, said second interrupt request flag having a reset input connected to receive a logical product signal between said interrupt acknowledge signal and the output of said second latch, so that said second interrupt request flag is cleared when the interrupt processing request corresponding to said second interrupt request flag is acknowledged, said first interrupt request flag having a reset input connected to receive a logical sum signal between said watchdog timer clear signal and a logical product signal between said interrupt acknowledge signal and the output of said first latch, so that, said first interrupt request flag is cleared when said watchdog timer clear signal is generated or when said watchdog timer processing request is acknowledged, said first and second latches of said priority level control unit operating to latch their input in response to said interrupt acknowledge signal, whereby, when said watchdog timer clear signal is generated, said first interrupt request flag and said first latch are cleared, so that said watchdog timer processing request is canceled.

Claim 3

A microcomputer claimed in claim 1 wherein said watchdog timer includes a watchdog timer counter for generating said watchdog timer processing request when said watchdog timer counter overflows, an internal control register written with a predetermined data by said central processing unit, and an internal decoder for decoding a content of said internal control register so as to preset said watchdog timer counter when said internal decoder decodes said predetermined data.

Claim 4

A microcomputer comprising: a bus (5); a central processing unit (10) coupled to said bus, and receiving an interrupt request signal (INTRQ 22) and generating an interrupt acknowledge signal (INTACK 23) after said central processing unit has received said interrupt request signal; a watchdog timer (11) coupled to said bus, and generating a watchdog timer interrupt processing request (INTWDT 21) when an overflow occurs in said watchdog timer, said watchdog timer being cleared by a watchdog timer clear signal (WDTCLR 24) generated by said central processing unit; an interrupt control circuit (12) coupled to said bus, and receiving said watchdog timer interrupt processing request, a non-maskable interrupt processing request (25a), and a maskable interrupt processing request (25b), said interrupt control circuit including: an interrupt request flag group having a first interrupt request flag (30a) set by said non-maskable interrupt processing request, a second interrupt request flag (30d) set by said watchdog timer interrupt processing request and a third interrupt request flag (30b) set by said maskable interrupt processing request, a priority level control unit (33) including a first latch (331a) having an input connected directly to an output of said first interrupt request flag (30a), a second latch (331d) having an input connected to an output of a first AND gate (332d) which has an inverted input connected to said output of said first interrupt request flag (30a) and a non-inverted input connected directly to an output of said second interrupt request flag (30d), a first OR gate (333d) having a pair of inputs connected to said outputs of said first and second interrupt request flags, a mask gate (344b) having a first input connected to an output of said third interrupt request flag (30b) and a second input connected to a mask flag signal (31b), a third latch (331b) having an input connected to an output of a second AND gate (232b) which has an inverted input connected to an output of said first OR gate and a non-inverted input connected to an output of said mask gate, and a second OR gate (333b) having a pair of inputs connected to said output of said first OR gate and said output of said mask gate, an output of said second OR gate generating the above mentioned interrupt request signal, each of said first, second and third latches operating to latch its input in response to said interrupt acknowledge signal and said watchdog timer clear signal, a vector generating unit coupled to an output of each of said first, second and third latches, for outputting through said bus to said central processing unit, a vector information corresponding to the latch latching an active signal, said first interrupt request flag having a reset input connected to an output of an AND gate (301a) which has a first input connected to the output of said first latch and a second input connected to receive said interrupt acknowledge signal, so that said first interrupt request flag is cleared when said non-maskable interrupt processing request is acknowledged, said third interrupt request flag having a reset input connected to an output of an AND gate (301b) which has a first input connected to the output of said third latch and a second input connected to receive said interrupt acknowledge signal, so that said third interrupt request flag is cleared when said maskable interrupt processing request is acknowledged, said second interrupt request flag having a reset input connected to an output of an OR gate (302) having a first input connected to receive said watchdog timer clear signal and a second input connected to an output of an AND gate (301d), which has a first input connected to the output of said second latch and a second input connected to receive said interrupt acknowledge signal, so that, when said watchdog timer interrupt processing request is acknowledged, said second interrupt request flag is cleared, and when said watchdog timer clear signal is generated, said second interrupt request flag and said second latch if set are cleared, so that said watchdog timer interrupt processing request is canceled before said watchdog timer interrupt processing request is actually executed.

Claim 5

A microcomputer comprising: a bus (5); a central processing unit (10) coupled to said bus, and receiving an interrupt request signal (INTRQ 22) and generating an interrupt acknowledge signal (INTACK 23) after said central processing unit has received said interrupt request signal; a watchdog timer (11) coupled to said bus, and generating a watchdog timer interrupt processing request (INTWDT 21) when an overflow occurs in said watchdog timer, said watchdog timer being cleared by a watchdog timer clear signal (WDTCLR 24) generated by said central processing unit; an interrupt control circuit (12) coupled to said bus, and receiving said watchdog timer interrupt processing request, a non-maskable interrupt processing request (25a), and a maskable interrupt processing request (25b), said interrupt control circuit including: an interrupt request flag group having a first interrupt request flag (30a) set by said non-maskable interrupt processing request, a second interrupt request flag (30d) set by said watchdog timer interrupt processing request and a third interrupt request flag (30b) set by said maskable interrupt processing request, a priority level control unit (33) including a first latch (331a) having an input connected directly to an output of said first interrupt request flag (30a), a second latch (331d) having an input connected to an output of a first AND gate (332d) which has an inverted input connected to said output of said first interrupt request flag (30a) and a non-inverted input connected directly to an output of said second interrupt request flag (30d), a first OR gate (333d) having a pair of inputs connected to said outputs of said first and second interrupt request flags, a mask gate (344b) having a first input connected to an output of said third interrupt request flag (30b) and a second input connected to a mask flag signal (31b), a third latch (331b) having an input connected to an output of a second AND gate (232b) which has an inverted input connected to an output of said first OR gate and a non-inverted input connected to an output of said mask gate, and a second OR gate (333b) having a pair of inputs connected to said output of said first OR gate and said output of said mask gate, an output of said second OR gate generating the above mentioned interrupt request signal, each of said first, second and third latches operating to latch its input in response to said interrupt acknowledge signal and said watchdog timer clear signal, a vector generating unit coupled to an output of each of said first, second and third latches, for outputting through said bus to said central processing unit, a vector information corresponding to the latch latching an active signal, said first interrupt request flag having a reset input connected to an output of an AND gate (301a) which has a first input connected to the output of said first latch and a second input connected to receive said interrupt acknowledge signal, so that said first interrupt request flag is cleared when said non-maskable interrupt processing request is acknowledged, said third interrupt request flag having a reset input connected to an output of an AND gate (301b) which has a first input connected to the output of said third latch and a second input connected to receive said interrupt acknowledge signal, so that said third interrupt request flag is cleared when said maskable interrupt processing request is acknowledged, said second interrupt request flag having a reset input connected to an output of an OR gate (302) having a first input connected to receive said watchdog timer clear signal and a second input connected to an output of an AND gate (301d), which has a first input connected to the output of said second latch and a second input connected to receive said interrupt acknowledge signal, so that, when said watchdog timer interrupt processing request is acknowledged, said second interrupt request flag is cleared, and when said watchdog timer clear signal is generated, said second interrupt request flag and said second latch if set are cleared, so that said watchdog timer interrupt processing request is canceled before said watchdog timer interrupt processing request is actually executed.