US5408320A
Expired / Lapsed
US
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Workpiece having alignment marks for positioning a pattern at a different pitch to be formed thereon, and method for fabricating the same
Assignee: Renesas Electronics Corp
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Filing: 1992-12-22
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Granted: 1995-04-18
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Expires: 2012-12-22
Abstract
Abstract A semiconductor wafer includes a top surface on which a semiconductor circuit pattern is to be fabricated, and a bottom surface on which alignment marks for positioning the semiconductor circuit pattern are arranged. The alignment marks are arranged at a predetermined pitch and in an arrangement that is not unique to the pattern formed on the top surface.
Inventors
- 👤 Soichi Katagiri
- 👤 Shigeo Moriyama
- 👤 Tsuneo Terasawa
- 👤 Masaaki Itou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:29
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7084; G01; G01B; G01B11/00; G01B11/26; G01B11/27; G01B11/272; G01D; G01D5/00; G01D5/26; G01D5/28; G01D5/30; G03F9/7088
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
58 words
A semiconductor wafer, comprising: a top surface on which a semiconductor circuit pattern is to be fabricated at a first predetermined pitch; and a bottom surface on which a plurality of alignment marks for positioning said semiconductor circuit pattern are arranged at a second predetermined pitch; wherein said second predetermined pitch is unrelated to the first predetermined pitch.
Claim 2
Dependent Claim
58 words
A semiconductor wafer, comprising: a top surface on which a semiconductor circuit pattern is to be fabricated at a first predetermined pitch; and a bottom surface on which a plurality of alignment marks for positioning said semiconductor circuit pattern are arranged at a second predetermined pitch; wherein said second predetermined pitch is unrelated to the first predetermined pitch.
Claim 3
Dependent Claim
18 words
A semiconductor wafer according to claim 1, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
Claim 4
Dependent Claim
15 words
A semiconductor wafer according to claim 1, wherein said top surface is a polished surface.
Claim 5
Independent Claim
74 words
A method for fabricating a semiconductor wafer, comprising the steps of: preparing a semiconductor substrate having a top surface and a bottom surface; and forming a plurality of marks on said bottom surface in accordance with a desired arrangement for positioning a semiconductor circuit pattern to be formed on said top surface; wherein the desired arrangement has a predetermined pitch that is unrelated to a pitch of the semiconductor circuit pattern to be formed.
Claim 6
Independent Claim
74 words
A method for fabricating a semiconductor wafer, comprising the steps of: preparing a semiconductor substrate having a top surface and a bottom surface; and forming a plurality of marks on said bottom surface in accordance with a desired arrangement for positioning a semiconductor circuit pattern to be formed on said top surface; wherein the desired arrangement has a predetermined pitch that is unrelated to a pitch of the semiconductor circuit pattern to be formed.
Claim 7
Dependent Claim
22 words
A method for fabricating a semiconductor wafer according to claim 4, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
Claim 8
Dependent Claim
20 words
A method for fabricating a semiconductor wafer according to claim 4, further comprising a step of polishing said top surface.
Claim 9
Dependent Claim
55 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed at a first predetermined pitch; and a bottom surface on which alignment marks for positioning said semiconductor chips are arranged at a second predetermined pitch; wherein said second predetermined pitch differs from the first predetermined pitch.
Claim 10
Dependent Claim
55 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed at a first predetermined pitch; and a bottom surface on which alignment marks for positioning said semiconductor chips are arranged at a second predetermined pitch; wherein said second predetermined pitch differs from the first predetermined pitch.
Claim 11
Dependent Claim
18 words
A semiconductor wafer according to claim 7, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
Claim 12
Dependent Claim
65 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement is unrelated to said first arrangement.
Claim 13
Dependent Claim
65 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement is unrelated to said first arrangement.
Claim 14
Dependent Claim
18 words
A semiconductor wafer according to claim 9, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
Claim 15
Dependent Claim
64 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement differs from said first arrangement.
Claim 16
Dependent Claim
64 words
A semiconductor wafer comprising: a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement differs from said first arrangement.
Claim 17
Dependent Claim
18 words
A semiconductor wafer according to claim 11, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
Claim 18
Dependent Claim
63 words
A workpiece comprising: a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement is unrelated to said first arrangement.
Claim 19
Dependent Claim
63 words
A workpiece comprising: a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement is unrelated to said first arrangement.
Claim 20
Dependent Claim
62 words
A workpiece comprising: a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement differs from said first arrangement.
Claim 21
Dependent Claim
62 words
A workpiece comprising: a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement; wherein said second arrangement differs from said first arrangement.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |