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US5408251A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory system for storing two-dimensional digitized image signals

Assignee: Quarterhill Inc
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Filing: 1993-10-29
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Granted: 1995-04-18
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Expires: 2013-10-29
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Abstract

Abstract Disclosed herein is a memory system for storing a two dimensional digitized image signal consisting of a plurality of pixels arranged in (2 M +X) columns and (2 N +Y) rows, wherein X and Y do not exceed 2 M-2 and 2 N-1 respectively, and M and N are integers, comprising: a virtual address generator for generating (M+N+2) bits of a virtual address having (M+1) bits of a horizontal address component representing said (2 M +X) columns and (N+1) bits of a vertical address component representing said (2 N +Y) rows; a memory, having storage locations of 2 M+N+1 , for storing the two dimensional digitized image signal, each of the storage locations capable of storing one pixel data therein and addressable by (M+N+1 bits) of a physical address; and address mapping circuitry for changing the virtual address to the physical address.

Inventors

  • 👤 Oh-Sang Kwon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-10 01:14
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/24; G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G06; G06F; G06F12/00; G06F12/02; G06F12/0207; H04N7/01; G09G2360/00; G09G2360/12

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 189 words
A memory system for storing a two dimensional digitized image signal consisting of a plurality of pixels arranged in (2 M +X) columns and (2 N +Y) rows, wherein X and Y do not exceed 2 M-2 and 2 N-1 , respectively, and M and N are positive integers, comprising: means for generating (M+N+2) bits of a virtual address having (M+1) bits of a horizontal address component representing said (2 M +X) columns and (N+1) bits of a vertical address component representing said (2 N +Y) rows; memory means, having storage locations of 2 M+N+1 , for storing the two dimensional digitized image signal, each of the storage locations capable of storing one pixel data therein and addressable by (M+N+1 bits) of a physical address; and mapping means for changing the virtual address to the physical address, wherein said mapping means utilizes a most significant bit of the horizontal address component and that of the vertical address component constituting the virtual address to regionalize the storage locations of said memory means into four regions so as to map the virtual address to the physical address on a region-by-region basis.
Claim 2
Dependent Claim 189 words
A memory system for storing a two dimensional digitized image signal consisting of a plurality of pixels arranged in (2 M +X) columns and (2 N +Y) rows, wherein X and Y do not exceed 2 M-2 and 2 N-1 , respectively, and M and N are positive integers, comprising: means for generating (M+N+2) bits of a virtual address having (M+1) bits of a horizontal address component representing said (2 M +X) columns and (N+1) bits of a vertical address component representing said (2 N +Y) rows; memory means, having storage locations of 2 M+N+1 , for storing the two dimensional digitized image signal, each of the storage locations capable of storing one pixel data therein and addressable by (M+N+1 bits) of a physical address; and mapping means for changing the virtual address to the physical address, wherein said mapping means utilizes a most significant bit of the horizontal address component and that of the vertical address component constituting the virtual address to regionalize the storage locations of said memory means into four regions so as to map the virtual address to the physical address on a region-by-region basis.
Claim 3
Dependent Claim 47 words
The system in accordance with claim 1, wherein the four regions are comprised of a first region having 2 M+N storage locations, a second region having 2 M+N-1 storage locations, a third region having 2 M+N-2 storage locations, and a fourth region having 2 M+N-3 storage locations.
Claim 4
Dependent Claim 80 words
The system in accordance with claim 2, wherein the first region is addressed by a most significant bit of a physical address, the second region is addressed by a most significant bit and its one adjacent bit of a physical address, the third region is addressed by a most significant bit and its two adjacent bits of a physical address and the fourth region is addressed by a most significant bit and its three adjacent bits of a physical address.

References Cited (Backward Citations)

US3974493A Cited
US4249172A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-17 1998-10-17 1999-04-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-17 2002-10-17 2003-04-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-17 2006-10-17 2007-04-18 $7700.00 Window Closed / Lapsed

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