Phase lock loop having a lock acquisition mode and method of operation therefor

Claim 2

A phase lock loop, having a first operating mode and a second operating mode, comprising an integrated circuit and a gain adjustment circuit, the integrated circuit comprising: a) phase detection means for detecting phase differences in said phase lock loop and operable in said first and second operating modes; b) an output for providing a desired frequency output; c) frequency adjustment means, coupled to said output and responsive to said phase detection means, for adjusting and canceling phase differences detected by said phase detection means and for providing an output signal to said output; d) filtering means, operable in said first and second operating modes, coupled between said phase detection means and said frequency adjustment means and responsive to said phase detection means; and g) an enable input for enabling operation of the integrated circuit; said gain adjustment circuit comprising: e) gain adjustment means coupled to said phase detection means for the gain control of said phase detection means and coupled to the enable input of the integrated circuit; wherein in response to an enable signal at the enable input, said gain adjustment means commences the controlled adjustment of the gain of said phase detection means and initiates a transition between said first and said second operating modes; and, in said first operating mode, i) said gain adjustment means adjusts the gain of said phase detection means to a relatively high value; and ii) said first operating mode is used to establish, to within a first tolerance of said desired frequency output, an initial lock acquisition in the phase lock loop; iii) said gain adjustment means adjusts the gain of said phase detection means in a gradual manner defined by a decreasing function; and iv) said second operating mode is used to establish a final lock acquisition at substantially the desired output frequency.

Claim 3

A phase lock loop in accordance with claim 1, wherein said first tolerance is 500 Hz.

Claim 4

A phase lock loop in accordance with claim 1, wherein the gradual decreasing function is an exponentially decreasing function.

Claim 5

A phase lock loop in accordance with claim 1, wherein the gradual decreasing function is characterised in that: a first portion of the function has a relatively slow rate of decrease in the slope thereof; and a second portion of the function has a relatively fast rate of decrease in the slope thereof.

Claim 6

A phase lock loop in accordance with claim 1, wherein lock acquisition is re-established within 5 milliseconds from said transition between operating modes.

Claim 7

A phase lock loop in accordance with claim 1, wherein the phase lock loop is implemented using fractional "N" integrated circuit technology.

Claim 8

A phase lock loop in accordance with claim 1, wherein the gain adjustment means comprises: a) selection means for selecting one of said first and said second operating modes; b) variable resistance means, responsive to said selection means, for varying the resistance of the gain adjustment means and thereby controllably adjusting the gain of said gain adjustment means; c) timing means, responsive to said selection means and said variable resistance means, for determining the rate at which the variable resistance means adjusts the gain.

Claim 9

A phase lock loop in accordance with claim 7, wherein: a) the variable resistance means comprises: i) a first resistor having relatively low resistance; ii) a second resistor having relatively high resistance; and iii) a transistor having a base electrode, collector electrode and an emitter electrode; wherein the second resistor is coupled in parallel with the series combination of said first resistor, said collector and said emitter; b) the selection means comprises a diode; and c) the timing means is a series coupled resistor-capacitor combination; wherein, an anode of the diode is coupled to the base of the transistor, and a mid-point of the resistor-capacitor combination of the timing means is coupled between said anode and said base electrode; the resistance of the circuit is reduced by the controlled introduction of the resistance provided by parallel resistor, as determined by the transistor; and such a reduction in the resistance causes the gain adjustment means to increase the gain of phase detector means.

Claim 12

A phase lock loop, operable in a first operating mode and a second operating mode, and having an integrated circuit with an enable input and a gain adjustment circuit; said integrated circuit comprising a) phase detection means for detecting phase differences in said phase lock loop and operable in said first and second operating modes; b) an output for providing a desired frequency output; c) frequency adjustment means, coupled to said output and responsive to said phase detection means, for adjusting and canceling phase differences detected by said phase detection means and for providing an output signal to said output; d) filtering means, operable in said first and second operating modes, coupled between said phase detection means and said frequency adjustment means and responsive to said phase detection means; and e) gain adjustment means responsive to said frequency output signal and coupled to said phase detection means for the gain control of said phase detection means; wherein said gain adjustment circuit causes said gain adjustment means to commence the controlled adjustment of the gain of said phase detection means in response to an enable signal at said integrated circuit enable input and initiates a transition between said first and said second operating modes; and, in said first operating mode, i) said gain adjustment means adjusts the gain of said phase detection means from a relatively low value to a relatively high value whereby said filtering means changes from having a relatively narrow bandwidth to having a relatively wide bandwidth; and ii) said first operating mode is used to establish, to within a first tolerance of said desired output frequency signal, an initial lock acquisition in the phase lock loop; whereafter, the transition between said operating modes causes the phase lock loop to temporarily lose lock acquisition obtained in said first operating mode, and operation in said second operating mode is characterised in that: iii) said gain adjustment means adjusts the gain of said phase detection means in a gradual manner defined by a decreasing function; and iv) said second operating mode is used to establish a final lock acquisition at substantially the desired output frequency.

Claim 13

A phase lock loop, operable in a first operating mode and a second operating mode, and having an integrated circuit with an enable input and a gain adjustment circuit; said integrated circuit comprising a) phase detection means for detecting phase differences in said phase lock loop and operable in said first and second operating modes; b) an output for providing a desired frequency output; c) frequency adjustment means, coupled to said output and responsive to said phase detection means, for adjusting and canceling phase differences detected by said phase detection means and for providing an output signal to said output; d) filtering means, operable in said first and second operating modes, coupled between said phase detection means and said frequency adjustment means and responsive to said phase detection means; and e) gain adjustment means responsive to said frequency output signal and coupled to said phase detection means for the gain control of said phase detection means; wherein said gain adjustment circuit causes said gain adjustment means to commence the controlled adjustment of the gain of said phase detection means in response to an enable signal at said integrated circuit enable input and initiates a transition between said first and said second operating modes; and, in said first operating mode, i) said gain adjustment means adjusts the gain of said phase detection means from a relatively low value to a relatively high value whereby said filtering means changes from having a relatively narrow bandwidth to having a relatively wide bandwidth; and ii) said first operating mode is used to establish, to within a first tolerance of said desired output frequency signal, an initial lock acquisition in the phase lock loop; whereafter, the transition between said operating modes causes the phase lock loop to temporarily lose lock acquisition obtained in said first operating mode, and operation in said second operating mode is characterised in that: iii) said gain adjustment means adjusts the gain of said phase detection means in a gradual manner defined by a decreasing function; and iv) said second operating mode is used to establish a final lock acquisition at substantially the desired output frequency.

Claim 14

A phase lock loop in accordance with claim 10, wherein the gradual decreasing function is an exponentially decreasing function.

Claim 15

A phase lock loop, having an integrated circuit and a gain adjustment circuit, the integrated circuit comprising: a) phase detection means for detecting phase differences in said phase lock loop; b) an output for providing a desired frequency output; c) frequency adjustment means, coupled to said output and responsive to said phase detection means, for adjusting and canceling phase differences detected by said phase detection means and for providing an output signal to said output; d) filtering means coupled between said phase detection means and said frequency adjustment means and responsive to said phase detection means; e) an enable input for enabling operation of the integrated circuit; and f) a gain control input for controlling the gain of the phase lock loop; said gain adjustment circuit comprising: g) a resistor-capacitor circuit coupled to said gain control input for the gain control of said phase detection means and responsively coupled to the enable input of the integrated circuit; wherein in response to an enable signal at the enable input, said gain adjustment circuit commences controlled adjustment of the gain of said phase detection means causing said gain adjustment means to adjust the gain of said phase detection means from a relatively low value to a relatively high value in a gradual manner defined by a said resistor-capacitor circuit.

Claim 16

A phase lock loop, having an integrated circuit and a gain adjustment circuit, the integrated circuit comprising: a) phase detection means for detecting phase differences in said phase lock loop; b) an output for providing a desired frequency output; c) frequency adjustment means, coupled to said output and responsive to said phase detection means, for adjusting and canceling phase differences detected by said phase detection means and for providing an output signal to said output; d) filtering means coupled between said phase detection means and said frequency adjustment means and responsive to said phase detection means; e) an enable input for enabling operation of the integrated circuit; and f) a gain control input for controlling the gain of the phase lock loop; said gain adjustment circuit comprising: g) a resistor-capacitor circuit coupled to said gain control input for the gain control of said phase detection means and responsively coupled to the enable input of the integrated circuit; wherein in response to an enable signal at the enable input, said gain adjustment circuit commences controlled adjustment of the gain of said phase detection means causing said gain adjustment means to adjust the gain of said phase detection means from a relatively low value to a relatively high value in a gradual manner defined by a said resistor-capacitor circuit.