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US5408192A
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Monolithic broadband phase shifting circuit for analog data signals
Assignee: International Business Machines Corp
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Filing: 1993-10-12
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Granted: 1995-04-18
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Expires: 2013-10-12
Abstract
Abstract An accurate phase shifting circuit providing two analog signals having a 90-degree phase shift between them from a single sampled-data input without the need for components external to a monolithic integrated circuit. A combination of two discrete-time circuits achieves the required 90-degree phase relationship over a broad frequency region. Several sample-and-hold circuits and multiplexors are used to produce two discrete-time versions of the analog input signal. Subtracting that older sample from the most-recent sample yields a forward difference signal and adding the most recent and the older samples produces a forward average signal. The phase difference between any single-frequency component of the forward difference and forward average signals is always 90 degrees. A pair of matched filters serves to reconstruct the sampled analog waveforms and to remove unwanted high-frequency noise in the +90° output signal.
Inventors
- 👤 James A. Bailey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:01
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/16; H03H11/22
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
266 words
A phase shifting circuit for differentiating an analog data signal to produce two analog quadrature signals separated from one another by a 90-degree phase shift, said circuit comprising: input means for accepting said analog data signal; multiphase clock input means for accepting a plurality N of sampling clock signals each having a fixed sampling interval T s and a fixed repetition rate F s =1/T s , wherein said sampling clock signals are offset from one another in time by one or more phase intervals T p =T s /N, wherein N>1 is a positive integer; a plurality N of sample-and-hold means coupled to said input means and to said multiphase clock input means, each said sample-and-hold means being for sampling and holding the value of said analog data signal responsive to a corresponding one of said plurality N of said sampling clock signals; two multiplexor means each having a multiplexor output and a plurality N of inputs each coupled to a corresponding one of said plurality N of sample-and-hold means, said each multiplexor means disposed for connecting one of said plurality N of sample-and-hold means to its multiplexor output responsive to a corresponding one of said plurality N of sampling clock signals; forward averaging means coupled to said two multiplexor means for adding the signals at said multiplexor outputs to create a forward average signal corresponding to a first said analog quadrature signal; and forward differencing means coupled to said two multiplexor means for subtracting the signals at said multiplexor outputs to create a forward difference signal corresponding to a second said analog quadrature signal.
Claim 2
Dependent Claim
266 words
A phase shifting circuit for differentiating an analog data signal to produce two analog quadrature signals separated from one another by a 90-degree phase shift, said circuit comprising: input means for accepting said analog data signal; multiphase clock input means for accepting a plurality N of sampling clock signals each having a fixed sampling interval T s and a fixed repetition rate F s =1/T s , wherein said sampling clock signals are offset from one another in time by one or more phase intervals T p =T s /N, wherein N>1 is a positive integer; a plurality N of sample-and-hold means coupled to said input means and to said multiphase clock input means, each said sample-and-hold means being for sampling and holding the value of said analog data signal responsive to a corresponding one of said plurality N of said sampling clock signals; two multiplexor means each having a multiplexor output and a plurality N of inputs each coupled to a corresponding one of said plurality N of sample-and-hold means, said each multiplexor means disposed for connecting one of said plurality N of sample-and-hold means to its multiplexor output responsive to a corresponding one of said plurality N of sampling clock signals; forward averaging means coupled to said two multiplexor means for adding the signals at said multiplexor outputs to create a forward average signal corresponding to a first said analog quadrature signal; and forward differencing means coupled to said two multiplexor means for subtracting the signals at said multiplexor outputs to create a forward difference signal corresponding to a second said analog quadrature signal.
Claim 3
Dependent Claim
9 words
The phase shifting circuit of claim 1 wherein N=3.
Claim 4
Dependent Claim
62 words
The phase shifting circuit of claim 2 further comprising: first filtering means coupled to said forward averaging means for removing some frequency components from said forward average signal to produce said first analog quadrature signal; and second filtering means coupled to said forward differencing means for removing some frequency components from said forward difference signal to produce said second analog quadrature signal.
Claim 5
Dependent Claim
29 words
The phase shifting circuit of claim 3 wherein said first and second filtering means each include a multipole low-pass filter circuit, said multipole low-pass filter circuits being substantially identical.
Claim 6
Dependent Claim
17 words
The phase shifting circuit of claim 4 wherein said circuit is implemented as a monolithic integrated circuit.
Claim 7
Dependent Claim
24 words
The phase shifting circuit of claim 1 wherein said forward averaging means and said forward differencing means each include a differential analog amplifier circuit.
Claim 8
Dependent Claim
9 words
The phase shifting circuit of claim 6 wherein N=3.
Claim 9
Dependent Claim
17 words
The phase shifting circuit of claim 7 wherein said circuit is implemented as a monolithic integrated circuit.
Claim 10
Dependent Claim
62 words
The phase shifting circuit of claim 1 further comprising: first filtering means coupled to said forward averaging means for removing some frequency components from said forward average signal to produce said first analog quadrature signal; and second filtering means coupled to said forward differencing means for removing some frequency components from said forward difference signal to produce said second analog quadrature signal.
Claim 11
Dependent Claim
29 words
The phase shifting circuit of claim 9 wherein said first and second filtering means each include a multipole low-pass filter circuit, said multipole low-pass filter circuits being substantially identical.
Claim 12
Dependent Claim
17 words
The phase shifting circuit of claim 1 wherein said circuit is implemented as a monolithic integrated circuit.
Claim 13
Dependent Claim
9 words
The phase shifting circuit of claim 11 wherein N=3.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |