Lateral resonant tunneling transistor with heterojunction barriers

Claim 2

A lateral resonant tunneling transistor formed at a face of semiconductor material, said transistor comprising: a quantized region formed between a first heterojunction tunnel barrier and a second heterojunction tunnel barrier, said barriers extending downwardly from said face; a source disposed adjacent to said first heterojunction tunnel barrier; a drain disposed adjacent to said second heterojunction tunnel barrier; and a gate structure disposed above said quantized region, said gate structure operable to adjust quantum states within said quantized region such that electrons may tunnel through said heterojunction tunnel barriers between said source and said drain upon the application of at least one predetermined potential to said gate structure.

Claim 3

The transistor of claim 1, and further comprising: a first semiconductor layer, said quantized region formed in said first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, and formed above and below said first semiconductor layer; and said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer.

Claim 4

The transistor of claim 2, wherein said heterojunction tunnel barriers further comprise semiconductor material regrown in two spaced-apart trenches formed downwardly from said face and through said first semiconductor layer.

Claim 5

The transistor of claim 3, wherein upper ends of said heterojunction tunnel barriers extend above sail face and join above said face.

Claim 6

The transistor of claim 3, wherein said gate structure comprises two gate contacts, each one of said gate contacts disposed over one of said heterojunction tunnel barriers.

Claim 7

The transistor of claim 3, wherein said heterojunction tunnel barriers and said quantized region each have first and second opposed lateral sidewalls, and further comprising: a semiconductor substrate on which said transistor is formed; a source contact for said source formed at said first sidewall to said semiconductor substrate; and a drain contact for said drain formed at said second sidewall to said semiconductor substrate.

Claim 8

The transistor of claim 6, wherein said semiconductor substrate is formed of a compound selected from the group of gallium arsenide and indium phosphide.

Claim 9

The transistor of claim 7, wherein said semiconductor substrate serves as one of said semiconductor barrier layers below said first semiconductor layer.

Claim 10

The transistor of claim 8, and further comprising an etch stop formed between said semiconductor substrate and said first semiconductor layer, and formed of a compound selected from the group consisting of aluminum arsenide, aluminum gallium arsenide and indium gallium arsenide.

Claim 11

The transistor of claim 6, wherein said first semiconductor layer is formed of a compound selected from the group of gallium arsenide and indium gallium arsenide.

Claim 12

The transistor of claim 6, wherein said semiconductor barrier layers are formed of a compound selected from the group consisting of aluminum gallium arsenide and indium aluminum arsenide.

Claim 13

The transistor of claim 6, wherein said face is formed of compound selected from the group consisting of gallium arsenide and indium gallium arsenide.

Claim 14

The transistor of claim 6, wherein said heterojunction tunnel barriers are formed of a compound selected from the group consisting of aluminum gallium arsenide, indium aluminum arsenide and indium phosphide.

Claim 15

The transistor of claim 6, and further comprising an etch stop formed between a bottom one of said semiconductor barriers and said first semiconductor layer, and formed of a compound selected from the group consisting of aluminum arsenide and indium phosphide.

Claim 16

The transistor of claim 2, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers by doping said upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a one-dimensional electron gas formed at an upper surface of said quantized region adjacent said upper one of said semiconductor barrier layers.

Claim 17

The transistor of claim 2, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers by doping said upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a zero-dimensional electron gas formed at an upper surface of said quantized region adjacent said upper one of said semiconductor barrier layers.

Claim 18

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, said first semiconductor layer formed between said two horizontal semiconductor barriers; a quantized region formed between two heterojunction tunnel barriers extending downwardly from said face, said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer and regrown on a trench surface, said trench formed downwardly from said face and through said first semiconductor layer; a second semiconductor layer formed between said heterojunction tunnel barriers and in which said quantized region is formed; a source disposed adjacent to one of said heterojunction tunnel barriers to be opposed to said quantized region; a drain disposed adjacent to the other of said heterojunction tunnel barriers to be opposed to said quantized region; and a gate structure above said quantized region, said gate structure operable to adjust quantum states within said quantized region such that electrons are able to tunnel through said quantized region between said source and said drain upon the application of at least one predetermined potential to said gate structure.

Claim 19

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, said first semiconductor layer formed between said two horizontal semiconductor barriers; a quantized region formed between two heterojunction tunnel barriers extending downwardly from said face, said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer and regrown on a trench surface, said trench formed downwardly from said face and through said first semiconductor layer; a second semiconductor layer formed between said heterojunction tunnel barriers and in which said quantized region is formed; a source disposed adjacent to one of said heterojunction tunnel barriers to be opposed to said quantized region; a drain disposed adjacent to the other of said heterojunction tunnel barriers to be opposed to said quantized region; and a gate structure above said quantized region, said gate structure operable to adjust quantum states within said quantized region such that electrons are able to tunnel through said quantized region between said source and said drain upon the application of at least one predetermined potential to said gate structure.

Claim 20

The transistor of claim 17, wherein said heterojunction tunnel barriers and said quantized region each have first and second opposed lateral sidewalls, and further comprising: a semiconductor substrate on which said transistor is formed; a source contact for said source formed at said first sidewall to said semiconductor substrate; and a drain contact for said drain formed at said second sidewall to said semiconductor substrate.

Claim 21

The transistor of claim 18, wherein said semiconductor substrate is formed of a compound selected from the group of gallium arsenide and indium phosphide.

Claim 22

The transistor of claim 19, wherein said semiconductor substrate serves as one of said semiconductor barrier layers below said first semiconductor layer.

Claim 23

The transistor of claim 20, and further comprising an etch stop formed between said semiconductor substrate and said first semiconductor layer, and formed of a compound selected from the group consisting of aluminum arsenide, aluminum gallium arsenide and indium gallium arsenide.

Claim 24

The transistor of claim 18, wherein said first semiconductor layer is formed of a compound selected from the group of gallium arsenide and indium gallium arsenide.

Claim 25

The transistor of claim 18, wherein said semiconductor barrier layers are formed of a compound selected from the group consisting of aluminum gallium arsenide and indium aluminum arsenide.

Claim 26

The transistor of claim 18, wherein said face is formed of compound selected from the group consisting of gallium arsenide and indium gallium arsenide.

Claim 27

The transistor of claim 18, wherein said heterojunction tunnel barriers are formed of a compound selected from the group consisting of aluminum gallium arsenide, indium aluminum arsenide and indium phosphide.

Claim 28

The transistor of claim 18, wherein said second semiconductor layer is formed of a compound selected from the group of gallium arsenide and indium gallium arsenide.

Claim 29

The transistor of claim 18, and further comprising an etch stop formed between a bottom one of said semiconductor barriers and said first semiconductor layer, and formed of a compound selected from the group consisting of aluminum arsenide and indium phosphide.

Claim 30

The transistor of claim 17, and further comprising a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers.

Claim 31

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a plurality of quantized regions formed in a row, each quantized region having an upper surface and formed between adjacent ones of a plurality of heterojunction tunnel barriers extending downwardly from said face; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of conductive gates disposed generally over said quantized regions said gates operable to adjust quantum states within said quantized regions such that electrons are able to tunnel through said barriers between said source and said drain upon the application of at least one predetermined potential to said gates.

Claim 32

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a plurality of quantized regions formed in a row, each quantized region having an upper surface and formed between adjacent ones of a plurality of heterojunction tunnel barriers extending downwardly from said face; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of conductive gates disposed generally over said quantized regions said gates operable to adjust quantum states within said quantized regions such that electrons are able to tunnel through said barriers between said source and said drain upon the application of at least one predetermined potential to said gates.

Claim 33

The transistor of claim 29, and further comprising: a first semiconductor layer, said quantized regions formed in said first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, and formed above and below said first semiconductor layer; and said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer.

Claim 34

The transistor of claim 30, wherein said heterojunction tunnel barriers further comprise semiconductor material regrown in a plurality of spaced-apart trenches formed downwardly from said face and through said first semiconductor layer.

Claim 35

The transistor of claim 31, wherein upper ends of said heterojunction tunnel barriers extend above said face and join above said face.

Claim 36

The transistor of claim 31, wherein said gates comprise a plurality of gate contacts, each one of said gate contacts disposed over one of said heterojunction tunnel barriers.

Claim 37

The transistor of claim 31, and further comprising: a semiconductor substrate over which said transistor is formed; a source contact for said source formed at a first sidewall, said first sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at one end of said row of quantized regions and opposed to said quantized regions to said semiconductor substrate; and a drain contact for said drain formed at a second sidewall, said second sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at the other end of said row of quantized regions and opposed to said quantized region to said semiconductor substrate.

Claim 38

The transistor of claim 30, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers by doping said upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a plurality of one-dimensional electron gas regions formed at said upper surfaces of said quantized regions adjacent said upper one of said semiconductor barrier layers.

Claim 39

The transistor of claim 30, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers by doping said upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a plurality of zero-dimensional electron gas regions formed at said upper surfaces of said quantized regions adjacent said upper one of said semiconductor barrier layers.

Claim 40

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, said first semiconductor layer formed between said two horizontal semiconductor barriers; a plurality of quantized regions formed in a row and having upper surfaces, each quantized region formed between adjacent ones of a plurality of heterojunction tunnel barriers extending downwardly from said face, such that each of said quantized regions is formed between two of said heterojunction tunnel barriers and each adjacent quantized region shams one of said heterojunction tunnel barriers, said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer and regrown on a plurality of trench surfaces, each of said trenches etched downwardly from said face and through said first semiconductor layer; a second semiconductor layer regrown on said heterojunction tunnel barriers, such that said quantized regions are formed between said heterojunction barriers, alternately in said second semiconductor layer and said first semiconductor layer; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of gates disposed over said quantized regions, said gate structures operable to adjust quantum states within said quantized regions such that electrons are able to tunnel through said quantized regions between said source and said drain upon the application of at least one predetermined potential to said gate structures.

Claim 41

A lateral resonant tunneling transistor formed at a face of semiconductor material, comprising: a first semiconductor layer; two horizontal semiconductor barrier layers having band gap energies higher than that of said first semiconductor layer, said first semiconductor layer formed between said two horizontal semiconductor barriers; a plurality of quantized regions formed in a row and having upper surfaces, each quantized region formed between adjacent ones of a plurality of heterojunction tunnel barriers extending downwardly from said face, such that each of said quantized regions is formed between two of said heterojunction tunnel barriers and each adjacent quantized region shams one of said heterojunction tunnel barriers, said heterojunction tunnel barriers formed of a semiconductor material having a higher band gap energy than that of said first semiconductor layer and regrown on a plurality of trench surfaces, each of said trenches etched downwardly from said face and through said first semiconductor layer; a second semiconductor layer regrown on said heterojunction tunnel barriers, such that said quantized regions are formed between said heterojunction barriers, alternately in said second semiconductor layer and said first semiconductor layer; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of gates disposed over said quantized regions, said gate structures operable to adjust quantum states within said quantized regions such that electrons are able to tunnel through said quantized regions between said source and said drain upon the application of at least one predetermined potential to said gate structures.

Claim 42

The transistor of claim 37, and further comprising: a semiconductor substrate over which said transistor is formed; a source contact for said source formed at a first sidewall, said first sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at one end of said row of quantized regions and opposed to said quantized regions to said semiconductor substrate; and a drain contact for said drain formed a second sidewall, said second sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at the other end of said row of quantized regions and opposed to said quantized region to said semiconductor substrate, said etched sidewalls formed by etching from said face to said substrate along said etched sidewalls.

Claim 43

The transistor of claim 37, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a plurality of one-dimensional electron gas regions formed at said upper surfaces of said quantized regions in said first semiconductor layer adjacent said upper one of said semiconductor barrier layers.

Claim 44

The transistor of claim 37, and further comprising: a two-dimensional electron gas layer formed at an upper surface of said first semiconductor layer adjacent an upper one of said semiconductor barrier layers by doping said upper one of said semiconductor barrier layers, said source and said drain contacting said two-dimensional electron gas layer outside of said heterojunction tunnel barriers; and a plurality of zero-dimensional electron gas regions formed at said upper surfaces of said quantized regions in said first semiconductor layer adjacent said upper one of said semiconductor barrier layers.

Claim 45

A lateral resonant tunneling transistor, comprising: a semi-insulating semiconductor substrate; a first semiconductor layer formed on said semi-insulating semiconductor substrate; a second semiconductor layer having a lower band gap energy than said first semiconductor layer and formed on said first semiconductor layer; a third semiconductor layer doped to be of a first conductivity type and having a higher band gap energy than said second semiconductor layer and formed on said second semiconductor layer forming a two-dimensional electron gas layer at an upper surface of said second semiconductor layer, said third semiconductor layer having an upper face opposite said second semiconductor layer; two heterojunction tunnel barriers extending downwardly from said upper face through said second semiconductor layer so as to form a quantized region between said heterojunction tunnel barriers; a source disposed adjacent to one of said heterojunction tunnel barriers to be opposed to said quantized region; a drain disposed adjacent to the other of said heterojunction tunnel barriers to be opposed to said quantized region; and a gate structure disposed over said quantized region, said gate structure operable to adjust quantum states within said quantized region such that electrons are able tunnel through said heterojunction tunnel barriers upon application of at least one predetermined potential to said gate structure.

Claim 46

A lateral resonant tunneling transistor, comprising: a semi-insulating semiconductor substrate; a first semiconductor layer formed on said semi-insulating semiconductor substrate; a second semiconductor layer having a lower band gap energy than said first semiconductor layer and formed on said first semiconductor layer; a third semiconductor layer doped to be of a first conductivity type and having a higher band gap energy than said second semiconductor layer and formed on said second semiconductor layer forming a two-dimensional electron gas layer at an upper surface of said second semiconductor layer, said third semiconductor layer having an upper face opposite said second semiconductor layer; two heterojunction tunnel barriers extending downwardly from said upper face through said second semiconductor layer so as to form a quantized region between said heterojunction tunnel barriers; a source disposed adjacent to one of said heterojunction tunnel barriers to be opposed to said quantized region; a drain disposed adjacent to the other of said heterojunction tunnel barriers to be opposed to said quantized region; and a gate structure disposed over said quantized region, said gate structure operable to adjust quantum states within said quantized region such that electrons are able tunnel through said heterojunction tunnel barriers upon application of at least one predetermined potential to said gate structure.

Claim 47

The transistor of claim 41, and further comprising a fourth semiconductor layer having a face opposite said third semiconductor layer and formed on said third semiconductor layer, and having a lower band gap energy than said third semiconductor layer, said heterojunction tunnel barriers extending downwardly from said face of said fourth semiconductor layer.

Claim 48

The transistor of claim 42, wherein said heterojunction tunnel barriers extend above said face and join above said face.

Claim 49

The transistor of claim 42, wherein said gate structure comprises two gate contacts, each one of said gate contacts disposed over one of said heterojunction tunnel barriers.

Claim 50

The transistor of claim 42, wherein said heterojunction tunnel barriers and said quantized region each have first and second opposed lateral sidewalls, and further comprising: a semiconductor substrate on which said transistor is formed; a source contact for said source formed at said first sidewall to said semiconductor substrate; and a drain contact for said drain formed at said second sidewall to said semiconductor substrate.

Claim 51

The transistor of claim 42, and further comprising: said heterojunction tunnel barriers formed of a semiconductor material grown along a trench surface, said trench etched downwardly from said face and through said second semiconductor layer; and a fifth semiconductor material, grown over said heterojunction tunnel barriers, in which said quantized region is formed.

Claim 52

The transistor of claim 46, wherein said heterojunction tunnel barriers and said quantized region each have first and second opposed lateral sidewalls, and further comprising: a semiconductor substrate on which said transistor is formed; a source contact for said source formed at said first sidewall to said semiconductor substrate; and a drain contact for said drain formed at said second sidewall to said semiconductor substrate.

Claim 53

A lateral resonant tunneling transistor, comprising: a semi-insulating semiconductor substrate; a first semiconductor layer formed on said semi-insulating semiconductor substrate; a second semiconductor layer having a lower band gap energy than said first semiconductor layer and formed on said first semiconductor layer; a third semiconductor layer doped to be of a first conductivity type and having a higher band gap energy than said second semiconductor layer and formed on said second semiconductor layer forming a two-dimensional electron gas layer at an upper surface of said second semiconductor layer, said third semiconductor layer having an upper face opposite said second semiconductor layer; a plurality of heterojunction tunnel barriers extending downwardly from said upper face through said second semiconductor layer so as to form a row of quantized regions between said heterojunction tunnel barriers, such that each of said quantized regions are formed between two of said heterojunction tunnel barriers and each adjacent quantized region shares one of said heterojunction tunnel barriers; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of gates disposed over said quantized regions, said gate structures operable to adjust quantum states within said quantized regions such that electrons are able tunnel through said heterojunction tunnel barriers upon application of at least one predetermined potential to said gate structures.

Claim 54

A lateral resonant tunneling transistor, comprising: a semi-insulating semiconductor substrate; a first semiconductor layer formed on said semi-insulating semiconductor substrate; a second semiconductor layer having a lower band gap energy than said first semiconductor layer and formed on said first semiconductor layer; a third semiconductor layer doped to be of a first conductivity type and having a higher band gap energy than said second semiconductor layer and formed on said second semiconductor layer forming a two-dimensional electron gas layer at an upper surface of said second semiconductor layer, said third semiconductor layer having an upper face opposite said second semiconductor layer; a plurality of heterojunction tunnel barriers extending downwardly from said upper face through said second semiconductor layer so as to form a row of quantized regions between said heterojunction tunnel barriers, such that each of said quantized regions are formed between two of said heterojunction tunnel barriers and each adjacent quantized region shares one of said heterojunction tunnel barriers; a source disposed adjacent to one of said heterojunction tunnel barriers located at one end of said row of quantized regions and opposed to said quantized regions; a drain disposed adjacent to one of said heterojunction tunnel barriers located at the other end of said row of quantized regions and opposed to said quantized regions; and a plurality of gates disposed over said quantized regions, said gate structures operable to adjust quantum states within said quantized regions such that electrons are able tunnel through said heterojunction tunnel barriers upon application of at least one predetermined potential to said gate structures.

Claim 55

The transistor of claim 48, and further comprising a fourth semiconductor layer having a face opposite said third semiconductor layer and formed on said third semiconductor layer, and having a lower band gap energy than said third semiconductor layer, said transistor formed at the face of said fourth semiconductor layer and said heterojunction tunnel barriers extending downwardly from said face of said fourth semiconductor layer.

Claim 56

The transistor of claim 49, wherein said heterojunction tunnel barriers further comprise semiconductor material regrown in a plurality of trenches etched downwardly from said face and through said second semiconductor layer.

Claim 57

The transistor of claim 50, wherein said gate structures comprise a plurality of gate contacts, each one of said gate contacts disposed over one of said heterojunction tunnel barriers.

Claim 58

The transistor of claim 50, and further comprising: a source contact for said source formed at a first sidewall, said first sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at one end of said row of quantized regions and opposed to said quantized regions to said semiconductor substrate; and a drain contact for said drain formed at a second sidewall, said second sidewall extending from said face adjacent to one of said heterojunction tunnel barriers at the other end of said row of quantized regions and opposed to said quantized region to said semiconductor substrate, said etched sidewalls formed by etching from said face to said substrate along said etched sidewalls.

Claim 59

The transistor of claim 48, wherein said heterojunction tunnel barriers are formed of a semiconductor material regrown along a plurality of trench surfaces, said trenches etched downwardly from said face and through said second semiconductor layer, and further comprising a fifth semiconductor layer, regrown over said heterojunction tunnel barriers, such that said quantized regions are formed between said heterojunction barriers, alternately in said fifth semiconductor layer and said second semiconductor layer.