Method for fabricating a semiconductor device having a shallow doped region

Claim 1

A method for fabricating a semiconductor device comprising: providing an N-type semiconductor substrate having a gate electrode overlying a gate dielectric layer; forming a material layer having a fluorinated-boron component overlying the gate electrode and the gate dielectric layer; diffusing boron atoms from the material layer through the dielectric layer and into the substrate in the presence of hydrogen to form lightly doped regions having a first junction depth in the substrate adjacent to the gate electrode, the lightly doped regions being characterized by a high concentration of boron atoms at the substrate surface and a uniform shallow doping profile in the substrate; etching the material layer to form sidewall spacers adjacent the gate electrode; and forming a heavily doped region in the substrate having a second junction depth using the sidewall spacers as a dopant mask wherein the second junction depth is farther removed from the substrate surface than the first junction depth.

Claim 2

A method for fabricating a semiconductor device comprising: providing an N-type semiconductor substrate having a gate electrode overlying a gate dielectric layer; forming a material layer having a fluorinated-boron component overlying the gate electrode and the gate dielectric layer; diffusing boron atoms from the material layer through the dielectric layer and into the substrate in the presence of hydrogen to form lightly doped regions having a first junction depth in the substrate adjacent to the gate electrode, the lightly doped regions being characterized by a high concentration of boron atoms at the substrate surface and a uniform shallow doping profile in the substrate; etching the material layer to form sidewall spacers adjacent the gate electrode; and forming a heavily doped region in the substrate having a second junction depth using the sidewall spacers as a dopant mask wherein the second junction depth is farther removed from the substrate surface than the first junction depth.

Claim 6

A method for fabricating a semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer thereon; depositing a first polysilicon layer overlying the gate dielectric layer; photolithographically patterning and etching the polysilicon layer to form a gate electrode; oxidizing the gate electrode to form an oxide layer thereon; depositing a second polysilicon layer overlying the gate electrode; implanting BF 2 ions into the second polysilicon layer; depositing an insulating layer overlying the second polysilicon layer; diffusing boron atoms from the second polysilicon layer through the gate dielectric layer and into the substrate to form lightly doped P-type source and drain regions having a first junction depth, the lightly doped regions being characterized by a high concentration of boron atoms at the substrate surface and a uniform shallow doping profile in the substrate; etching the second polysilicon layer to form sidewall spacers on the gate electrode; and implanting dopant atoms into the substrate to form heavily doped source and drain regions adjacent to the lightly doped source and drain regions having a second junction depth wherein the second junction depth is farther removed from the substrate surface than the first junction depth.

Claim 7

A method for fabricating a semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer thereon; depositing a first polysilicon layer overlying the gate dielectric layer; photolithographically patterning and etching the polysilicon layer to form a gate electrode; oxidizing the gate electrode to form an oxide layer thereon; depositing a second polysilicon layer overlying the gate electrode; implanting BF 2 ions into the second polysilicon layer; depositing an insulating layer overlying the second polysilicon layer; diffusing boron atoms from the second polysilicon layer through the gate dielectric layer and into the substrate to form lightly doped P-type source and drain regions having a first junction depth, the lightly doped regions being characterized by a high concentration of boron atoms at the substrate surface and a uniform shallow doping profile in the substrate; etching the second polysilicon layer to form sidewall spacers on the gate electrode; and implanting dopant atoms into the substrate to form heavily doped source and drain regions adjacent to the lightly doped source and drain regions having a second junction depth wherein the second junction depth is farther removed from the substrate surface than the first junction depth.