US5406518A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration
Assignee: Industrial Technology Research Institute
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Filing: 1994-02-08
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Granted: 1995-04-11
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Expires: 2014-02-08
Abstract
Abstract The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.
Inventors
- 👤 Cheng-Yun Sun
- 👤 Yung-Jung Jan
- 👤 Ching-Hsiang Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:03
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/0736; G06F2205/00; G06F2205/10; G06F2205/104
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
234 words
A variable length delay circuit for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said delay circuit comprising: a single integrated data storage means for storing said input data therein; a delay address generating means including a timing control block for controlling the operation of said variable delay circuit wherein said timing control block utilizing a normal system clock signal and a higher-frequency clock signal at a multiple frequency rate of said normal system clock signal; said delay address generating means further including an address a write control means for controlling the writing of said input data to a write-address in said data storage means, said delay address generating means further including a delay address means for receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address wherein each of said addresses covering the entire range of said storing means; an output means for reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each of said output data representing said corresponding input data delayed by said corresponding variable-length delay; and said output means further includes a latching block controlled by said higher-frequency clock signal thus enabling simultaneous output of said plurality of output data according to said normal system clock signal.
Claim 2
Dependent Claim
234 words
A variable length delay circuit for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said delay circuit comprising: a single integrated data storage means for storing said input data therein; a delay address generating means including a timing control block for controlling the operation of said variable delay circuit wherein said timing control block utilizing a normal system clock signal and a higher-frequency clock signal at a multiple frequency rate of said normal system clock signal; said delay address generating means further including an address a write control means for controlling the writing of said input data to a write-address in said data storage means, said delay address generating means further including a delay address means for receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address wherein each of said addresses covering the entire range of said storing means; an output means for reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each of said output data representing said corresponding input data delayed by said corresponding variable-length delay; and said output means further includes a latching block controlled by said higher-frequency clock signal thus enabling simultaneous output of said plurality of output data according to said normal system clock signal.
Claim 3
Dependent Claim
43 words
The variable length delay circuit of claim 1 wherein: said write control means further includes an input multiplexing means controlled by said higher-frequency clock signal thus enabling simultaneous input of a plurality of said input data to be delayed by said delay circuit.
Claim 4
Dependent Claim
49 words
The variable length delay circuit of claim 2 wherein: said delay address means further includes a delay multiplexing means controlled by said higher-frequency clock signal thus enabling simultaneous input of a plurality of multiple sets of said variable-length delays for generating said delay output addresses in said storage means.
Claim 5
Dependent Claim
50 words
The variable length delay circuit of claim 3 wherein: said delay address means further includes a delay address computing means including adding or subtracting means and latches controlled by said higher-frequency clock signal thus enabling simultaneous computing said delay output addresses in said storage means by using said variable-length delays.
Claim 6
Dependent Claim
52 words
The variable length delay circuit of claim 4 wherein: said delay address means further includes a plurality of registers for simultaneous receiving and temporarily storing said plurality of multiple sets of variable-length delays to be used by said delay address computing means for computing said delay output addresses in said storage means.
Claim 7
Dependent Claim
365 words
A variable length delay circuit for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said delay circuit comprising: a single integrated data storage means for storing said input data therein; a delay address generating means including a timing control block for controlling the operation of said variable delay circuit, a write control means for controlling the writing of said input data to a write-address in said data storage means, and a delay address means for receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address wherein each of said delay output addresses covering the entire range of said storing means; said timing control block utilizing a normal system clock signal and a higher-frequency clock signal at a multiple frequency rate of said normal system clock signal; said write control means further including a multiplexing means controlled by said higher-frequency clock signal for enabling simultaneous input of a plurality of said input data to be delayed by said delay circuit; said delay address means further including a delay address computing means including adding or subtracting means and latches controlled by said higher-frequency clock signal thus enabling simultaneous computing said delay output addresses in said storage means by using said variable-length delays; said delay address means further including a multiplexing means controlled by said higher-frequency clock signal thus enabling simultaneous input of a plurality of multiple sets of said variable-length delays for generating said delay output addresses in said storage means; said delay address means further includes a plurality of registers for simultaneous receiving and temporary storing said plurality of multiple sets of variable-length delays for computing said delay output addresses in said storage means; an output means for reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each output data representing said corresponding input data delayed by said corresponding variable-length delay; and said output means further includes a latching block controlled by said higher-frequency clock signal thus enabling simultaneous output of said plurality of output data according to said normal system clock signal.
Claim 8
Dependent Claim
365 words
A variable length delay circuit for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said delay circuit comprising: a single integrated data storage means for storing said input data therein; a delay address generating means including a timing control block for controlling the operation of said variable delay circuit, a write control means for controlling the writing of said input data to a write-address in said data storage means, and a delay address means for receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address wherein each of said delay output addresses covering the entire range of said storing means; said timing control block utilizing a normal system clock signal and a higher-frequency clock signal at a multiple frequency rate of said normal system clock signal; said write control means further including a multiplexing means controlled by said higher-frequency clock signal for enabling simultaneous input of a plurality of said input data to be delayed by said delay circuit; said delay address means further including a delay address computing means including adding or subtracting means and latches controlled by said higher-frequency clock signal thus enabling simultaneous computing said delay output addresses in said storage means by using said variable-length delays; said delay address means further including a multiplexing means controlled by said higher-frequency clock signal thus enabling simultaneous input of a plurality of multiple sets of said variable-length delays for generating said delay output addresses in said storage means; said delay address means further includes a plurality of registers for simultaneous receiving and temporary storing said plurality of multiple sets of variable-length delays for computing said delay output addresses in said storage means; an output means for reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each output data representing said corresponding input data delayed by said corresponding variable-length delay; and said output means further includes a latching block controlled by said higher-frequency clock signal thus enabling simultaneous output of said plurality of output data according to said normal system clock signal.
Claim 9
Independent Claim
151 words
A method for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said method comprising the steps of: (a) controlling the operation of a variable delay circuit by the use of a timing control block; (b) storing said input data in a single integrated data storage means by employing a write control means for writing said input data to a write-address; (c) receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address by employing a delay address generating means wherein each of said addresses covering the entire range of said storing means; and (d) reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each of said output data representing said corresponding input data delayed by said corresponding variable-length delay.
Claim 10
Independent Claim
151 words
A method for generating a plurality of output data each representing a corresponding input data delayed by a variable length, said method comprising the steps of: (a) controlling the operation of a variable delay circuit by the use of a timing control block; (b) storing said input data in a single integrated data storage means by employing a write control means for writing said input data to a write-address; (c) receiving a plurality of variable length delays to generate for each of said delays a corresponding delay output address by employing a delay address generating means wherein each of said addresses covering the entire range of said storing means; and (d) reading a plurality of output data from said data storage means at each of said delay output addresses for outputting said output data wherein each of said output data representing said corresponding input data delayed by said corresponding variable-length delay.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-04-10 | 1998-10-10 | 1999-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-10 | 2002-10-10 | 2003-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-10 | 2006-10-10 | 2007-04-11 | $7700.00 | Window Closed / Lapsed |