US5406472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-lane controller
Assignee: ZF International UK Ltd
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Filing: 1992-12-03
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Granted: 1995-04-11
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Expires: 2012-12-03
Abstract
Abstract A multi-lane controller providing redundancy comprises two lanes. Each lane comprises an input/output interface, a data flow controller and a control data processor. Each data flow controller receives input data from and supplies output data to both input/output interfaces. The information exchange between each lane does not rely on the proper operation of either the control data processor or data flow controller of any of the lanes.
Inventors
- 👤 John R. Simmons
- 👤 Peter D. Smout
- 👤 James Tipton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:48
CPC Classifications
G; G05; G05B; G05B9/00; G05B9/02; G05B9/03
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
471 words
A multi-lane controller comprising: a first lane; a second lane; and a lane selector; said first lane comprising a first control data processor, a first data flow controller, a first signal path, a first input/output interface connected to said first data flow controller by said first signal path, a first lane input, and a first lane output, said first control data processor being connected via said first data flow controller, said first signal path, and said first input/output interface to said first lane input and said first lane output; said second lane comprising a second control data processor, a second data flow controller, a second signal path, a second input/output interface connected to said second data flow controller by said second signal path, a second lane input, and a second lane output, said second control data processor being connected via said second data flow controller, said second signal path, and said second input/output interface to said second lane input and said second lane output; said first data flow controller having first and second inputs connected to said first and second signal paths, respectively, to receive input data from said first and second input/output interfaces, respectively, and to supply the input data to said first control data processor, said second data flow controller having third and fourth inputs connected to said first and second signal paths, respectively, to receive the input data from said first and second input/output interfaces, respectively, and to supply the input data to said second control data processor, said first and second data flow controllers being arranged to supply output data from said first and second control data processors to said first and second input/output interfaces, respectively; said data flow controller of each one of said lanes comprising first to fourth read/write memories having respective write inputs and read outputs, said first read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of said one lane, said second read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of an other of said lanes, said third read/write memory having a write input connected to said interface of said one lane and a read output connected to said control data processor of said one lane, and said fourth read/write memory having a write input connected to said interface of said other lane and a read output connected to said control data processor of said one lane; and said lane selector being arranged to permit the supply of output data to said lane output of one of said first and second lanes and to inhibit the supply of output data to said lane output of another of said first and second lanes.
Claim 2
Dependent Claim
471 words
A multi-lane controller comprising: a first lane; a second lane; and a lane selector; said first lane comprising a first control data processor, a first data flow controller, a first signal path, a first input/output interface connected to said first data flow controller by said first signal path, a first lane input, and a first lane output, said first control data processor being connected via said first data flow controller, said first signal path, and said first input/output interface to said first lane input and said first lane output; said second lane comprising a second control data processor, a second data flow controller, a second signal path, a second input/output interface connected to said second data flow controller by said second signal path, a second lane input, and a second lane output, said second control data processor being connected via said second data flow controller, said second signal path, and said second input/output interface to said second lane input and said second lane output; said first data flow controller having first and second inputs connected to said first and second signal paths, respectively, to receive input data from said first and second input/output interfaces, respectively, and to supply the input data to said first control data processor, said second data flow controller having third and fourth inputs connected to said first and second signal paths, respectively, to receive the input data from said first and second input/output interfaces, respectively, and to supply the input data to said second control data processor, said first and second data flow controllers being arranged to supply output data from said first and second control data processors to said first and second input/output interfaces, respectively; said data flow controller of each one of said lanes comprising first to fourth read/write memories having respective write inputs and read outputs, said first read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of said one lane, said second read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of an other of said lanes, said third read/write memory having a write input connected to said interface of said one lane and a read output connected to said control data processor of said one lane, and said fourth read/write memory having a write input connected to said interface of said other lane and a read output connected to said control data processor of said one lane; and said lane selector being arranged to permit the supply of output data to said lane output of one of said first and second lanes and to inhibit the supply of output data to said lane output of another of said first and second lanes.
Claim 3
Dependent Claim
55 words
A controller as claimed in claim 1, wherein said lane selector is arranged, upon a detection of a fault in one of said lanes, to inhibit the supply of output data to said output lane of said one lane and to permit the supply of output data to said output lane of said other lane.
Claim 4
Dependent Claim
37 words
A controller as claimed in claim 1, wherein said first and second data flow controllers are arranged to supply output data from said first and second control data processors to said second and first input/output interfaces, respectively.
Claim 5
Dependent Claim
70 words
A controller as claimed in claim 3, wherein said lane selector is arranged, upon detection of a fault in control data processor of said one of said lanes and a fault in said input/output interface of said other lane, to permit the supply of output data from said control data processor of said other lane via said input/output interface of said one lane to said output of said one lane.
Claim 6
Dependent Claim
21 words
A controller as claimed in claim 1, wherein each of said first and second input/output interfaces comprises an interface data processor.
Claim 7
Dependent Claim
29 words
A controller as claimed in claim 5, further comprising a sample rate clock for each of said interface data processors and synchronising means for synchronising said sample rate clocks.
Claim 8
Dependent Claim
41 words
A controller as claimed in claim 6, further comprising a respective watch dog timer provided for each of said control data processors and said interface data processors, each of said respective watchdog timers having an output connected to said lane selector.
Claim 9
Dependent Claim
45 words
A controller as claimed in claim 1, wherein said first and second control data processors are arranged, upon detection of a fault in a part of one of said first and second data flow controllers, to inhibit the use of data transferred via said part.
Claim 10
Dependent Claim
44 words
A controller as claimed in claim 1, wherein said first and second input/output interfaces are arranged, upon detection of a fault in a part of one of said first and second data flow controllers, to inhibit the use of data transferred via said part.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-10 | 1998-10-10 | 1999-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-10 | 2002-10-10 | 2003-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-10 | 2006-10-10 | 2007-04-11 | $7700.00 | Window Closed / Lapsed |