EP0211500A2
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EP
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Data control system for digital automatic flight control system channel with plural dissimilar data processing
Assignee: Honeywell Inc
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Filing: 1986-06-24
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Granted: —
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Expires: 2006-06-24
Abstract
Abstract A direct memory access (DMA) system (17) with a single bus (24) architecture for controlling data transfers and storage between plural digital processors (11, 12) and plural Input/Output devices (13-16). Limiters (18, 19) are included for disabling access to the bus (24) of a processor (11, 12) whose access time exceeds a predetermined time interval. A time governor (122, 124) is included to suppress processor access to the bus (24) when total processor access time in a data communicating cycle has exceeded a predetermined time interval. The input and output devices (13-16) are coupled to the bus (24) through interface isolation circuits (20) which prevent faults in the input and output devices from propagating to the system to cause total system failure. An input or output device (13-16) fault can only result in erroneous data being provided to a location of the DMA memory (17) reserved for the faulted device. The DMA memory (17) is protected by a Write-Protect Decoding Circuit (50) which prevents processor writing into prohibited areas of the memory (30).
Inventors
- 👤 Larry James Yount
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 00:26
CPC Classifications
G; G05; G05D; G05D1/00; G05D1/0055; G05D1/0077; G05B; G05B9/00; G05B9/02; G05B9/03; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F11/004; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/076
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
147 words
A channel (10) for an automatic flight control system comprising a set of input devices (13-16), a set of output devices (13-16), a first digital processor (11), a second digital processor (12) and a data control system (17) intercoupling the set of input devices, the set of output devices, the first digital processor and the second digital processor for transferring data signals, address signals and control signals therebetween, characterised in that the channel further comprises first limiter means (18) associated with the first digital processor (11) for disabling access of the first digital processor to the data control system (17) whenever the first digital processor maintains access thereto for greater than a first predetermined time interval, and second limiter means (19) associated with the second digital processor (12) for diabling access of the second digital processor maintains access thereto for greater than a second predetermined time interval.
Claim 2
Dependent Claim
147 words
A channel (10) for an automatic flight control system comprising a set of input devices (13-16), a set of output devices (13-16), a first digital processor (11), a second digital processor (12) and a data control system (17) intercoupling the set of input devices, the set of output devices, the first digital processor and the second digital processor for transferring data signals, address signals and control signals therebetween, characterised in that the channel further comprises first limiter means (18) associated with the first digital processor (11) for disabling access of the first digital processor to the data control system (17) whenever the first digital processor maintains access thereto for greater than a first predetermined time interval, and second limiter means (19) associated with the second digital processor (12) for diabling access of the second digital processor maintains access thereto for greater than a second predetermined time interval.
Claim 3
Dependent Claim
132 words
A channel according to claim 1, provides a request that the first digital processor (11) provides a request signal to the data control system (17) for requesting access thereto and the data control system provdes an enable signal to the first digital proceesor for enabling access of the first digital processor to the data control system, and in that the first limited means (18) comprises counter means (72) enabled by the enable signal for timing the first predetermined time interval, latch means (74) responsive to the counter means for providing a disabling signal when the counter means attains the first predetermined time interval, and first gate means (62) responsive to the disabling signal and the request signal for blocking transmission of the request signal when the latch means provides the disabling signal.
Claim 4
Dependent Claim
101 words
A channel according to claim 1 or 2, characterised in that the data control system (17) operates in iterative data communication cycles and in that the data control system includes governor means (122, 124) for suppressing access of the first and second digital processors (11, 12) to the data control system when the time the first and second processors have had access to the data control system during a data communication cycle exceeds a third predetermined time interval, the governor means effecting said suppression until all of the input and output devices (13-16) have had access to the data control system.
Claim 5
Dependent Claim
122 words
A channel according to claim 3, characterised in that each of the first and second digital processors (11, 12) provides a request signal to the data control system (17) for requesting access thereto, and the data control system provides enable signals to the first and second digital processors for enabling access thereof, respectively, to the data control system, and in that the governor means comprises counter means (122) responsive to the enable signals for enabling the counter means when the first and second digital processors have access to the data control system, and second gate means (124) responsive to the counter means and to the request signals for blocking the request signals when the counter means attains said third predetermined time interval.
Claim 6
Dependent Claim
74 words
A channel according to claim 4, characterised in that the data control system (17) includes a device counter (96) for providing a sequence of device code signals corresponding to the input and output devices (13-16) respectively, the device counter providing a maximum count signal when the device counter has counted through a complete sequence of the device codes, the maximum count signal being coupled to the governor counter (122) for clearing the governor counter.
Claim 7
Dependent Claim
62 words
A channel according to claim 4, characterised in that the second gate means (124) includes means for deferring the suppression of access of the first and second digital processors (11, 12) to the data control system (17) if either the first or second digital processor has access to the data control system the said governor counter attains said third predetermined time interval.
Claim 8
Dependent Claim
116 words
A channel according to any of the claims 1 to 4, characterised in that the data control system comprises (17) bus (24) means intercoupling the set of input devices (13-16), the set of output devices (13-16), the first digital processor (11) and the second digital processor (12) for conveying data signals, address signals and control signals therebetween, and memory means (30) coupled to the bus means for receiving data from, and providing data to, the first digital processor, the second digital processor, the set of input devices, and the set of output devices via the bus means, the data control system comprising a direct memory acces (DMA) system (17) with respect to the memory means (30).
Claim 9
Dependent Claim
94 words
A channel according to claim 7, characterised in that the DMA system (17) includes a device counter (96) for providing a sequence of device code signals corresponding to the input and output devices (13-16), respectively, and a plurality of interface isolation circuits (20) coupling the input and output devices to the bus means (24) so as to prevent a fault which occurs in an input or output device from propagating into the channel except for erroneous data being entered into a location of the memory means (30) assigned to the device having the fault.
Claim 10
Dependent Claim
90 words
A channel according to claim 8, characterised in that each input and output device (13-16) provides a local device code signal, designating the device, to the interface isolation circuit associated therewith, and each interface isolation circuit (20) includes comparator (105) means responsive to the device code signals from the device counter (96) and to the local device code signal from the input or output device associated therewith for providing an enabling signal to the interface isolation circuit when one of the device code signals matches the local device code signal.
Claim 11
Dependent Claim
76 words
A channel according to claim 8 or 9, characterised in that each interface isolation circuit (20) includes specifier generator means (108) for providing a sequence of specifier signals corresponding to the data items, respectively, associated with the input or output device (13-16) coupled to the interface isolation circuit, and specifier buffer means (111), enabled in response to the enabling signal and responsive to the specifier signals, for conveying the specifier signals to the bus means (24).
Claim 12
Dependent Claim
44 words
A channel according to claim 10, characterised in that each interface isolation circuit (20) includes data buffer means (113), enabled in response to the enabling signal, for coupling data signals between the input and output device (13-16) associated therewith and the bus means (24).
Claim 13
Dependent Claim
79 words
A channel according to claim 10, characterised in that DMA system (17) further includes address mapping means (35) responsive to the device code signals and to the specifier signals for providing a map address signal in accordance with the device code signal and the specifier signal applied thereto for addressing the memory means (30) to access a location therein reserved for the data item from the input or output device designated by the specifier signal and device code signal.
Claim 14
Dependent Claim
93 words
A channel according to any of claims 10 to 12, characterised in that the bus means (24) comprises a data bus (33) and an address bus (34), the data bus coupling the memory means (30), the address mapping means (35) and the interface isolation circuits (20) for conveying data signals between the memory means and the interface isolation circuits, and for conveying the specifier signals to the address mapping means, and the address bus (34) coupling the address mapping means (35) to the memory means (30) for conveying the map addres signals thereto.
Claim 15
Dependent Claim
37 words
A channel according to claim 7, characterised in that the bus means (24) comprises a data bus (33) and an address bus (34) coupling the first and second digital processors (11, 12) with the memory means (30).
Claim 16
Dependent Claim
57 words
A channel according to claim 14, characterised in that the memory means (30) comprises first and second memory sections (51, 52) associated with the first and second digital processors, respectively, so that only the first digital processor can write into the first memory section and only the second digital processor can write into the second memory section.
Claim 17
Dependent Claim
71 words
A channel according to claim 15, characterised in that the DMA system (17) includes write-protection circuit means (50) coupled to the address bus (34) for preventing the first digital processor (11) from writing into the second memory section (52) and the second digital processor (12) from writing into the first memory section (51) in accordance with the address signals conveyed on the address bus from the first and second digital processors.
Claim 18
Dependent Claim
35 words
A channel according to claim 15 or 16, characterised in that the memory means (30) includes a third memory section (54) into which neither the first (11) nor the second (12) digital processor can write.
Claim 19
Dependent Claim
34 words
A channel according to claim 17, characterised in that the DMA system (17) is so constructed and arranged as to write the same data item into plural sections (51-54) of the memory means (30).
Claim 20
Dependent Claim
70 words
A channel according to any of claims 14 to 18, characterised in that the DMA system (17) provides enable signals to the first and second digital processors (11, 12), respectively, the DMA system further including buffer means (116, 118, 120) coupling the first and second digital processors to the data bus (33) and address bus (34), the enable signals being coupled to the buffer means for enabling the buffer means.
Claim 21
Dependent Claim
48 words
A channel according to any of claims 7 to 19, characterised in that the DMA system (17) further includes sequencer means for sequentially providing access to the bus means (24) for each of the input and output devices (13-16) and the first and second digital processors (11, 12).
Claim 22
Dependent Claim
18 words
An automatic flight control system having at least one channel in accordance with any of the preceding claims.
References Cited (Backward Citations)
US4117459A
Cited
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