Technique and method for asynchronous scan design

Claim 2

A scannable RS latch for use in asynchronous designs, the scannable RS latch having inputs being responsive to SET and RESET signals and first and second outputs for providing first and second complementary output signals, comprising: first multiplexer means being responsive to a first set of control signals for selectively passing signal SET and signal RESET, or signal SCANIN to an output of said first multiplexer means; first latch means being responsive to a clock signal for storing a logic value of a signal appearing at said output of said first multiplexer means, said first latch means having first and second inputs and first and second outputs, said first and second inputs of said first latch means coupled to said output of said first multiplexer means; second latch means being responsive to said clock signal for storing logic values of signals appearing at said first and second outputs of said first latch means, said second latch means having first and second inputs and first and second outputs, said first and second inputs of said second latch means coupled to said first and second outputs of said first latch means, said first and second outputs of said second latch means for providing the first and second complementary output signals, said first output of said second latch means for providing a SCANOUT signal.

Claim 3

The scannable RS latch according to claim 1 further including second multiplexer means within said second latch means for alternately placing the scannable RS latch in a normal mode operation and a test mode operation.

Claim 4

The scannable RS latch according to claim 1 wherein said first multiplexer means includes: a first multiplexer having first and second inputs, a select input and an output, said first input of said first multiplexer coupled for receiving the SET signal, said second input coupled for receiving the RESET signal, said select input of said first multiplexer coupled for receiving a sample signal; and a second multiplexer having first and second inputs, a select input and an output, said first input of said second multiplexer coupled to said output of said first multiplexer, said second input of said second multiplexer coupled for receiving said SCANIN signal, said select input of said second multiplexer coupled for receiving a shift signal, said output of said second multiplexer coupled to said first latch means.

Claim 5

The scannable RS latch according to claim 1 wherein said first latch means includes: logic means being responsive to said clock signal for passing said logic value appearing at said output of said first multiplexer means, said logic means having first and second outputs for providing complementary logic values thereat; and a first RS latch having first and second inputs and first and second outputs, said first and second inputs of said first RS latch coupled to said first and second outputs of said logic means, said first and second outputs of said RS latch respectively coupled to said first and second inputs of said second latch means.

Claim 6

The scannable RS latch according to claim 2 wherein said second latch means includes: logic means being responsive to said clock signal for passing said logic values appearing at said output of said first multiplexer means, said logic means having first and second outputs for providing complementary logic values thereat; and a first RS latch having first and second inputs and first and second outputs, said first and second inputs of said first RS latch coupled to said first and second outputs of said logic means, said first and second outputs of said RS latch respectively coupled for providing the first and second complementary output signals.

Claim 7

The scannable RS latch according to claim 5 wherein said second multiplexer means includes: a first multiplexer having first and second inputs, a select input and an output, said first input of said first multiplexer coupled for receiving the SET signal, said second input coupled to said first output of said logic means of said second latch means, said select input of said first multiplexer coupled for receiving a test control signal, said output of said first multiplexer coupled to said first input of said RS latch of said second latch means; and a second multiplexer having first and second inputs, a select input and an output, said first input of said second multiplexer coupled for receiving the RESET signal, said second input of said second multiplexer coupled to said second output of said logic means of said second latch means, said select input of said second multiplexer coupled for receiving said test control signal, said output of said second multiplexer coupled to said second input of said RS latch of said second latch means.

Claim 8

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch; second multiplexer means responsive to a sample signal for sampling the SET signal, said second multiplexer means having first and second inputs, a select input and an output, said first input of said second multiplexer means coupled to receive a SCANIN signal, said second input of said second multiplexer means coupled to receive the SET signal, said select input of said second multiplexer means coupled to receive said sample signal; and a first flipflop having a data input, a clock input and first and second outputs, said data input of said first flipflop coupled to said output of said second multiplexer means, said clock input coupled to receive a clock signal, said first and second outputs of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means, said second output of said first flipflop providing a SCANOUT signal.

Claim 9

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch; second multiplexer means responsive to a sample signal for sampling the SET signal, said second multiplexer means having first and second inputs, a select input and an output, said first input of said second multiplexer means coupled to receive a SCANIN signal, said second input of said second multiplexer means coupled to receive the SET signal, said select input of said second multiplexer means coupled to receive said sample signal; and a first flipflop having a data input, a clock input and first and second outputs, said data input of said first flipflop coupled to said output of said second multiplexer means, said clock input coupled to receive a clock signal, said first and second outputs of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means, said second output of said first flipflop providing a SCANOUT signal.

Claim 10

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch; second multiplexer means responsive to a sample signal for sampling the SET signal, said second multiplexer means having first and second inputs, a select input and an output, said first input of said second multiplexer means coupled to receive a SCANIN signal, said second input of said second multiplexer means coupled to receive the SET signal, said select input of said second multiplexer means coupled to receive said sample signal; a first flipflop having a data input, a clock input and a first output, said data input of said first flipflop coupled to said output of said third multiplexer means, said clock input coupled to receive a clock signal, said first output of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means; third multiplexer means responsive to said sample signal for sampling the RESET signal, said third multiplexer means having first and second inputs, a select input and an output, said first input of said third multiplexer means coupled to said first output of said first flip for receiving said SCANIN signal, said second input of said second multiplexer means coupled to receive the RESET signal, said select input of said second multiplexer means coupled to receive said sample signal; and a second flipflop having a data input, a clock input and a first output, said data input of said second flipflop coupled to said output of said third multiplexer means, said clock input coupled to receive said clock signal, said first output of said second flipflop coupled for providing said SCANIN signal to said first multiplexer means, said first output of said second flipflop providing a SCANOUT signal.

Claim 11

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch; second multiplexer means responsive to a sample signal for sampling the SET signal, said second multiplexer means having first and second inputs, a select input and an output, said first input of said second multiplexer means coupled to receive a SCANIN signal, said second input of said second multiplexer means coupled to receive the SET signal, said select input of said second multiplexer means coupled to receive said sample signal; a first flipflop having a data input, a clock input and a first output, said data input of said first flipflop coupled to said output of said third multiplexer means, said clock input coupled to receive a clock signal, said first output of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means; third multiplexer means responsive to said sample signal for sampling the RESET signal, said third multiplexer means having first and second inputs, a select input and an output, said first input of said third multiplexer means coupled to said first output of said first flip for receiving said SCANIN signal, said second input of said second multiplexer means coupled to receive the RESET signal, said select input of said second multiplexer means coupled to receive said sample signal; and a second flipflop having a data input, a clock input and a first output, said data input of said second flipflop coupled to said output of said third multiplexer means, said clock input coupled to receive said clock signal, said first output of said second flipflop coupled for providing said SCANIN signal to said first multiplexer means, said first output of said second flipflop providing a SCANOUT signal.

Claim 12

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch, an output of said first multiplexer means for providing a SCANOUT signal; a first flipflop having a data input, a clock input and a first output, said data input of said first flipflop coupled for receiving said SCANIN signal, said clock input coupled to receive a clock signal, said first output of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means; and a second flipflop having a data input, a clock input and a first output, said data input of said second flipflop coupled to said first output of said first flipflop for receiving said SCANIN signal, said clock input coupled to receive said clock signal, said first output of said second flipflop coupled for providing said SCANIN signal and an inverted SCANIN signal to said first multiplexer means.

Claim 13

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: first multiplexer means responsive to a TEST signal for selectively passing a SET and a RESET signal to said first and second inputs of the RS latch or a SCANIN signal to the first and second inputs of the RS latch, an output of said first multiplexer means for providing a SCANOUT signal; a first flipflop having a data input, a clock input and a first output, said data input of said first flipflop coupled for receiving said SCANIN signal, said clock input coupled to receive a clock signal, said first output of said first flipflop coupled for providing said SCANIN signal to said first multiplexer means; and a second flipflop having a data input, a clock input and a first output, said data input of said second flipflop coupled to said first output of said first flipflop for receiving said SCANIN signal, said clock input coupled to receive said clock signal, said first output of said second flipflop coupled for providing said SCANIN signal and an inverted SCANIN signal to said first multiplexer means.

Claim 16

The method of scanning an RS latch according to claim 10 further including a step of sampling said RESET and SET signals.

Claim 17

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: a first flipflop having a data input, a clock input and first and second complementary outputs, said data input being coupled for receiving a SCANIN signal, said clock input being coupled for receiving a clock signal, said first output passing said SCANIN signal, said second output providing an inverted SCANIN signal; and multiplexer means coupled for receiving a SET and a RESET signal at first and second inputs and passing said SET and RESET signals to first and second outputs in response to a first state of a TEST signal, said first and second outputs of said multiplexer means being respectively coupled to the first and second inputs of the RS latch, said multiplexer means further being coupled for receiving said SCANIN signal and said inverted SCANIN signal at third and fourth inputs and passing said SCANIN signal and said inverted SCANIN signal to said first and second outputs in response to a second state of said TEST signal, said first output of said multiplexer means providing a SCANOUT signal.

Claim 18

A circuit for use with an RS latch for making the RS latch scannable, the RS latch having first and second inputs and first and second outputs, the circuit comprising: a first flipflop having a data input, a clock input and first and second complementary outputs, said data input being coupled for receiving a SCANIN signal, said clock input being coupled for receiving a clock signal, said first output passing said SCANIN signal, said second output providing an inverted SCANIN signal; and multiplexer means coupled for receiving a SET and a RESET signal at first and second inputs and passing said SET and RESET signals to first and second outputs in response to a first state of a TEST signal, said first and second outputs of said multiplexer means being respectively coupled to the first and second inputs of the RS latch, said multiplexer means further being coupled for receiving said SCANIN signal and said inverted SCANIN signal at third and fourth inputs and passing said SCANIN signal and said inverted SCANIN signal to said first and second outputs in response to a second state of said TEST signal, said first output of said multiplexer means providing a SCANOUT signal.