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US5406099A Expired / Lapsed US ⏱️ 0.0 years remaining

High electron mobility transistor

Assignee: Sony Corp
•
Filing: 1994-04-20
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Granted: 1995-04-11
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Expires: 2014-04-20
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Abstract

Abstract A compound semiconductor device including a substrate; a first epitaxial layer formed on the substrate, the first epitaxial layer having an impurity concentration of 1×10 15 ≦p≦1×10 16 (cm -3 ); and a second epitaxial layer formed on the first epitaxial layer for allowing travel of two-dimensional electrons, the second epitaxial layer having an impurity concentration of n≦1×10 14 (cm -3 ) and p≦1×10 14 (cm -3 ). With the device disclosed, it is difficult for a short channel effect due to a reduction in gate length to occur, thereby ensuring high characteristics of the compound semiconductor device.

Inventors

  • 👤 Shigeru Hiramatsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6349

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 144 words
A HEMT compound semiconductor device, comprising: a substrate; a first epitaxial layer formed on said substrate, said first epitaxial layer having a p-type impurity concentration of 1×10 15 (cm -3 ); a second epitaxial layer formed on said first epitaxial layer for allowing travel of two-dimensional electrons in an electron channel located near an upper edge of said second epitaxial layer, said second epitaxial layer having an impurity concentration of n≦1×10 14 (cm -3 ) and p≦1×10 14 (cm -3 ); an intrinsic layer on the second epitaxial layer; an n-type electron supplying layer on the intrinsic layer; a gate electrode on the n-type electron supplying layer; and a source electrode connecting to the n-type electron supplying layer on one side of the gate electrode and a drain electrode connecting to the n-type electron supplying layer on the other side of the gate electrode.
Claim 2
Dependent Claim 144 words
A HEMT compound semiconductor device, comprising: a substrate; a first epitaxial layer formed on said substrate, said first epitaxial layer having a p-type impurity concentration of 1×10 15 (cm -3 ); a second epitaxial layer formed on said first epitaxial layer for allowing travel of two-dimensional electrons in an electron channel located near an upper edge of said second epitaxial layer, said second epitaxial layer having an impurity concentration of n≦1×10 14 (cm -3 ) and p≦1×10 14 (cm -3 ); an intrinsic layer on the second epitaxial layer; an n-type electron supplying layer on the intrinsic layer; a gate electrode on the n-type electron supplying layer; and a source electrode connecting to the n-type electron supplying layer on one side of the gate electrode and a drain electrode connecting to the n-type electron supplying layer on the other side of the gate electrode.
Claim 3
Dependent Claim 16 words
The semiconductor device according to claim 1 wherein the second epitaxial layer is formed of GaAs.
Claim 4
Dependent Claim 16 words
The semiconductor device according to claim 1 wherein the second epitaxial layer is formed of InGaAs.
Claim 5
Dependent Claim 36 words
The semiconductor device according to claim 1 wherein another n-type layer is provided on the n-type electron supplying layer between the source electrode and electron supplying layer and the drain electrode and the electron supplying layer.

References Cited (Backward Citations)

JPS62298179A Cited
US4788156A Cited
US5028968A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-10 1998-10-10 1999-04-11 $2000.00 Window Closed / Lapsed
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