Patent US5404526A successfully refreshed from Google Patents.
US5404526A
Expired / Lapsed
US
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Improved method for accessing machine state information
Assignee: Round Rock Research LLC
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Filing: 1992-10-20
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Granted: 1995-04-04
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Expires: 2012-10-20
Abstract
Abstract A method is provided for overcoming the slow speed of accessing machine state information from a device under test using boundary scan technology. The method minimizes the total number of words sent over the lengthy communications path by filtering out intermediary data. The method enables transfers of results to take place while other boundary scan circuitry commands are executing. Firmware is provided that transforms a boundary scan circuitry controller into a debug controller. Building the debug functions into the system makes it possible to have debug capability from module level integration all the way to system level integration.
Inventors
- 👤 Daniel G. Dosch
- 👤 Otis A. Bundy
- 👤 Robert Whyms, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:20
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2733; G06F11/2205; G06F11/2221
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
218 words
A processor-implemented method for accessing machine state information from a device under test using boundary scan circuitry, wherein said device under test is provided with a debug controller, said debug controller including at least a portion of the command repertoire for said boundary scan circuitry, comprising the steps of: a) initiating a boundary scan circuity command by means of an external controller, said external controller sending an initiation instruction to a test set; b) processing said initiation instruction at said test set and transmitting said boundary scan circuitry command from said test set to a console provided in said device under test; c) transmitting said boundary scan circuitry command from said console to said debug controller; d) processing said boundary scan circuitry command in said debug controller and transmitting said portion of the command repertoire to a target configured gate array on said device under test, said configured gate array processing said portion of the command repertoire and transmitting an intermediary report of machine state information to said debug controller; e) processing said intermediary report of machine state information at said debug controller by transmitting follow-up commands to said target configured gate array on said device under test as needed; and f) transmitting a final report of machine state information from said debug controller to said external controller.
Claim 2
Dependent Claim
218 words
A processor-implemented method for accessing machine state information from a device under test using boundary scan circuitry, wherein said device under test is provided with a debug controller, said debug controller including at least a portion of the command repertoire for said boundary scan circuitry, comprising the steps of: a) initiating a boundary scan circuity command by means of an external controller, said external controller sending an initiation instruction to a test set; b) processing said initiation instruction at said test set and transmitting said boundary scan circuitry command from said test set to a console provided in said device under test; c) transmitting said boundary scan circuitry command from said console to said debug controller; d) processing said boundary scan circuitry command in said debug controller and transmitting said portion of the command repertoire to a target configured gate array on said device under test, said configured gate array processing said portion of the command repertoire and transmitting an intermediary report of machine state information to said debug controller; e) processing said intermediary report of machine state information at said debug controller by transmitting follow-up commands to said target configured gate array on said device under test as needed; and f) transmitting a final report of machine state information from said debug controller to said external controller.
Claim 3
Dependent Claim
20 words
The method of claim 1 comprising the further step of providing a debug monitor routine resident in said debug controller.
Claim 4
Dependent Claim
29 words
The method of claim 1 comprising the further steps of providing overlays for each requested portion of said command repertoire and providing said overlays resident in a wake-up prom.
Claim 5
Dependent Claim
39 words
The method of claim 1 comprising the further step of providing a firmware segment in said boundary scan circuitry, said firmware segment containing said portion of said command repertoire, said portion of said command repertoire being downloaded as needed.
References Cited (Backward Citations)
US5155732A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |