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US5404472A
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Parallel processing apparatus and method capable of switching parallel and successive processing modes
Assignee: Hitachi Ltd
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Filing: 1993-11-10
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Granted: 1995-04-04
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Expires: 2013-11-10
Abstract
Abstract When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.
Inventors
- 👤 Kenichi Kurosawa
- 👤 Shigeya Tanaka
- 👤 Yasuhiro Nakatsuka
- 👤 Tadaaki Bandoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/30181; G06F9/30189; G06F9/3802; G06F9/3824; G06F9/3836; G06F9/3842; G06F9/3861; G06F9/3867
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
A parallel processing apparatus, comprising: a program counter for indicating instructions to be read out from a memory; a plurality of instruction registers for respectively storing instructions therein indicated by said program counter; a plurality of arithmetic units for executing arithmetic operations; means for controlling said plurality of arithmetic units to effect either parallel processing of a plurality of consecutive instructions read out from an address of said memory indicated by said program counter in said plurality of arithmetic units, or successive processing of n consecutive instructions, read out from an address of said memory indicated by said program counter, in which said n consecutive instructions correspond to said plurality of arithmetic units, respectively, when the instruction is supplied to each of the arithmetic units from the instruction register.
Claim 2
Dependent Claim
129 words
A parallel processing apparatus, comprising: a program counter for indicating instructions to be read out from a memory; a plurality of instruction registers for respectively storing instructions therein indicated by said program counter; a plurality of arithmetic units for executing arithmetic operations; means for controlling said plurality of arithmetic units to effect either parallel processing of a plurality of consecutive instructions read out from an address of said memory indicated by said program counter in said plurality of arithmetic units, or successive processing of n consecutive instructions, read out from an address of said memory indicated by said program counter, in which said n consecutive instructions correspond to said plurality of arithmetic units, respectively, when the instruction is supplied to each of the arithmetic units from the instruction register.
Claim 3
Dependent Claim
39 words
A parallel processing apparatus according to claim 1, said means for controlling said plurality of arithmetic units in response to either a processing state alteration instruction or control signal through pin which has said parallel processing apparatus from outside.
Claim 4
Dependent Claim
32 words
A parallel processing apparatus according to claim 1, further comprising means for controlling said program counter to increment either m or 1 according to a value indicated by said processing state flag.
Claim 5
Dependent Claim
23 words
A parallel processing apparatus according to claim 1, further including a sequencer for controlling said program counter, said sequencer comprising a wired-logic circuit.
Claim 6
Dependent Claim
24 words
A parallel processing apparatus according to claim 1, further including a sequencer for controlling said program counter, said sequencer being implemented by a microprogram.
References Cited (Backward Citations)
US4942525A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |