Method for interleaving computer disk data input-out transfers with permuted buffer addressing

Claim 1

In a computer system including a processor having select logic, data and address I/O bus, random access memory (RAM), provisions for the attachment of one or more peripheral devices into the system data and address I/O bus, and an I/O subsystem for increasing utilization of the computer system I/O bandwidth during data transfers with the peripheral devices, said I/O subsystem comprising; address and control buses, buffer select and address control logic; and at least two I/O devices each having data buffers, said I/O devices and data buffers connected to said processor I/O buses and transferring data when requested by said processor select logic, said buffer select logic connected to enable said I/O device data buffers for transfer of data between said I/O device buffers and I/O data bus, wherein the data buffer of the first of said I/O devices is connected to a lower portion of said processor I/O data bus and the data buffer of the second said I/O devices is connected to an upper portion of said processor I/O data bus; and wherein the address control logic includes circuitry for permuting the selected address locations of said random access memory during data transfers between said I/O device data buffers and random access memory; and wherein said address control logic comprises: means for writing a first data short word from said second I/O device to said random access memory low half word at a first address offset by a fixed value; means for simultaneously writing a first data short word from said first I/O device to said random access memory low half word at the first address and a second data short word from said second I/O device to said random access memory high half word at the first address offset by the fixed value; means for simultaneously writing the next short word from said first and second I/O devices to said random access memory high half word at the first address and low half word at the next address offset by the fixed value, respectively; means for simultaneously writing subsequent short words from said first and second I/O devices to said random access memory low and high half words alternately at subsequent addresses for data from said first I/O device and at subsequent addresses offset by the fixed value for data from said second I/O device; and means for writing a last short word from said first I/O device to said random access memory high half word at a last address.

Claim 3

A method for a computer system including a processor, data and address I/O bus, random access memory (RAM), provisions for the attachment of one or more peripheral devices into the system data and address I/O bus, wherein a processing means increases utilization of the computer system I/O bandwidth during data transfers with the peripheral devices, said method comprising the steps of: writing a first data short word from a second I/O device to a random access memory low half word at a first address offset by a fixed value; simultaneously writing a first data short word from a first I/O device to said random access memory low half word at the first address and a second data short word from said second I/O device to said random access memory high half word at the first address offset by the fixed value; simultaneously writing the next short words from said first and second I/O devices to said random access memory high half word at the first address and low half word at the next address offset by the fixed value, respectively; simultaneously writing subsequent short words from said first and second I/O devices to said random access memory low and high half words alternately at subsequent addresses for data from said first I/O device and at subsequent addresses offset by the fixed value for data from said second I/O device; and writing a last short word from said first I/O device to said random access memory high half word at a last address.

Claim 4

A method for a computer system including a processor, data and address I/O bus, random access memory (RAM), provisions for the attachment of one or more peripheral devices into the system data and address I/O bus, wherein a processing means increases utilization of the computer system I/O bandwidth during data transfers with the peripheral devices, said method comprising the steps of: writing a first data short word from a second I/O device to a random access memory low half word at a first address offset by a fixed value; simultaneously writing a first data short word from a first I/O device to said random access memory low half word at the first address and a second data short word from said second I/O device to said random access memory high half word at the first address offset by the fixed value; simultaneously writing the next short words from said first and second I/O devices to said random access memory high half word at the first address and low half word at the next address offset by the fixed value, respectively; simultaneously writing subsequent short words from said first and second I/O devices to said random access memory low and high half words alternately at subsequent addresses for data from said first I/O device and at subsequent addresses offset by the fixed value for data from said second I/O device; and writing a last short word from said first I/O device to said random access memory high half word at a last address.