Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames

Claim 2

A desynchronizer for use with a digital communication network, the digital communication network transmitting information in frames containing payloads, the payloads containing data residing within said frames, each payload having a pointer position identifying its starting location within a frame, and wherein the data within each payload may contain at least one stuff bit, the desynchronizer adjusting a read data clock rate for reading the payload data, the desynchronizer comprising: a) means for receiving the transmitted information and for extracting the pointer position and stuff bit information therefrom; b) means for generating a write clock rate; c) means connected to the extracting means, for extracting the payload data from the frames of data based upon the write clock rate; d) means connected to the payload data extracting means, for storing the payload data within an addressable write/read elastic store module accessible by corresponding write and read addresses, said module having a nominal relative center position representing the nominal difference between the write and read addresses; e) means for reading payload data from the elastic store module based upon the read data clock rate and for generating a serial output of said read data; f) means connected to the elastic store module, for determining the difference between the write and read addresses (W-R) of the elastic store module; g) means for accumulating the W-R difference for a plurality of samples so that the W-R difference has a predetermined bit resolution; h) means connected to the pointer position and stuff bit information extracting means, for scaling the pointer position and stuff bit information so as to correspond in bit resolution to the accumulated W-R difference, and means for digitally high pass filtering the scaled pointer position and stuff bit information so that changes in the pointer position and stuff bit information from frame to frame are passed to an output of the filtering means at which said changes then decay exponentially to zero; i) means for subtracting, at a bit resolution corresponding to the bit resolution of the accumulation means and the digital high pass filtering means, the output of the digital high pass filtering means from the output of the accumulating means to determine a number representative of their difference; and j) means for receiving said representative number and for generating the read data clock rate whose frequency is adjusted according to this representative number so as to re-center the elastic store module to its nominal center position; whereby changes in pointer position and stuff bit information are adjusted with high resolution such that the elastic store module is returned to its nominal relative center position without generating rapid phase changes and jitter on the read data clock rate.

Claim 3

A desynchronizer as defined in claim 1, wherein the scaling means connected to the pointer position and stuff bit information extracting means includes a lookup table which contains values corresponding to changes in the elastic store write addresses based upon pointer position within the frame and changes in pointer position from frame to frame for all possible pointer positions within the frame, and wherein said digital high pass filtering means retrieves an elastic store write address change value from the lookup table based upon pointer position within the frame and the change in the pointer position.

Claim 4

A desynchronizer as defined in claim 2, wherein the digital high pass filtering means comprises a register having an input and an output, the output corresponding to the output of the digital high pass filtering means, the register for storing the output value of the digital high pass filtering means, a multiplier for receipt of said output value and for multiplying it by a value less than one, and a summer for summing the scaled pointer position and stuff bit information, plus the value from the multiplier output, the result of the summer defining the input to the register.

Claim 5

A desynchronizer as defined in claim 3, wherein the means for accumulating the W-R difference performs the accumulation at a rate equal to a multiple of the number of bytes in one frame.

Claim 6

A desynchronizer as defined in claim 4, wherein the means for receiving the representative number and for generating the read data rate includes means for generating a variable duty cycle signal having a constant frequency, whose duty cycle is proportional to the W-R difference from the elastic store module, which is further used to control the read data clock rate.

Claim 7

A desynchronizer as defined in claim 5, wherein the means for receiving the representative number and for generating the read data clock rate comprises a loop filter which receives the variable duty cycle signal and a variable controlled oscillator connected to the loop filter as part of a wide bandwidth phase-locked loop having a bandwidth greater than that of the digital high pass filtering means connected to the pointer position and stuff bit information extracting means.

Claim 8

A desynchronizer as defined in claim 6, further comprising a threshold comparator module for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a first threshold value and if so, setting a status bit indicative of this occurrence, said status bit communicated with the digital high pass filtering means to increase the bandwidth of said digital high pass filtering means.

Claim 9

A desynchronizer as defined in claim 7, wherein the threshold comparator further comprises means for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a second threshold value greater than the first threshold value, and if so for setting a second status bit which is communicated to the digital high pass filtering means to disable all inputs to said digital high pass filtering means and thereby cause rapid movement of the W-R value back to the nominal relative center of the elastic store module.

Claim 10

A desynchronizer as defined in claim 8, wherein the threshold means has means for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a third threshold value, and if so to set a third status bit, said status bit communicated to the elastic store module so as to cause the elastic store module to reset its W-R value to the nominal relative center position.

Claim 11

A desynchronizer as defined in claim 7, wherein said status bit from the threshold comparator increases the bandwidth of the digital high pass filtering means by decreasing the value of the multiplier.

Claim 12

A desynchronizer as defined in claim 10, wherein the value of the multiplier for a bandwidth of the digital high pass filtering means is set forth in the following table: TABLE ______________________________________ BANDWIDTH VALUE OF MULTIPLIER ______________________________________ 0.1 Hz 0.9999214633 0.2 Hz 0.999842933 1.0 Hz 0.999214910 3.0 Hz 0.997646579 10.0 Hz 0.992176780 ______________________________________

Claim 13

A desynchronizer as defined in claim 2, further comprising adjusting means connected to the output of the digital high pass filtering means for presenting an output to the means for subtracting the output of the digital high pass filtering means from the output of the accumulating means, such that the subtraction has a value of zero with a one byte peak-to-peak sawtooth waveform at the pointer arrival rate when continuous pointers are received so as to re-center the elastic store module when a constant frequency offset between nodes of the network exist.

Claim 14

A desynchronizer as defined in claim 12, wherein said adjusting means comprises a multiplier, a summer, and a register, wherein the multiplier has a value less than one and is connected to the output of the register, so as to yield a bandwidth which is much lower than the bandwidth of the digital high pass filtering means.

Claim 15

A desynchronizer as defined in claim 1, further comprising adjusting means connected to the output of the digital high pass filtering means for presenting an output to the means for subtracting the output of the digital high pass filtering means from the output of the accumulating means, such that the output of the adjusting means is equal to the long term average output of the high pass filtering means, which when added to the output of the digital high pass filtering means at the subtractor, causes the average elastic store position to re-center when continuous pointer activity is present due to a constant frequency offset between nodes of the network.

Claim 16

A desynchronizer as defined in claim 2, further comprising a threshold comparator module for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a first threshold value and if so, setting a status bit indicative of this occurrence, said status bit communicated with the digital high pass filtering means so as to increase the bandwidth of said digital high pass filtering means.

Claim 17

A desynchronizer as defined in claim 1, further comprising a threshold comparator module for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a first threshold value and if so, setting a status bit indicative of this occurrence, said status bit communicated with the digital high pass filtering means so as to increase the bandwidth of said digital high pass filtering means.

Claim 18

A desynchronizer for use with a digital communication network, the digital communication network transmitting information in a plurality of frames, each frame comprising a payload containing data, wherein the starting location of each payload is defined by a pointer position, and wherein the data within each payload may contain at least one stuff bit, the desynchronizer for adjusting a read data clock rate for reading the payload data, the desynchronizer comprising: a) means for receiving the transmitted information and for extracting the pointer position of the payload, stuff bit information, as well as the payload data from the frames of data received; b) means connected to the extracting means, for storing the payload data within an addressable write/read elastic store module accessible by corresponding write and read addresses, said module having a nominal relative center position representing the nominal difference between the write and read addresses; c) means for reading payload data from the elastic store based upon the read data clock rate, said reading means generating a serial output of said read data; d) means connected to the elastic store, for determining the difference between the write and read addresses (W-R) of the elastic store; e) a lookup table which contains values corresponding to changes in the elastic store write addresses based upon pointer position within the frame and changes in pointer position between frames, for all possible pointer positions within the frame; f) means connected to the pointer position and stuff bit information extracting means and to the lookup table, for digitally high pass filtering the stuff bit information and a value from the lookup table determined by the pointer position within the frame and the change in the pointer position, so that changes in the elastic store write address based upon pointer position Within the frame and changes to the pointer position and the stuff bit information from frame to frame are passed to the output of the filtering means at which said changes then decay exponentially to zero; g) means for subtracting the output of the digital high pass filtering means from the W-R address difference to determine a number representative of the difference between the output of the digital high pass filtering means and the W-R address difference; and h) means for using the representative number to generate the read data clock rate whose frequency is adjusted according to this representative number.

Claim 19

A desynchronizer for use with a digital communication network, the digital communication network transmitting information in a plurality of frames, each frame comprising a payload containing data, wherein the starting location of each payload is defined by a pointer position, and wherein the data within each payload may contain at least one stuff bit, the desynchronizer for adjusting a read data clock rate for reading the payload data, the desynchronizer comprising: a) means for receiving the transmitted information and for extracting the pointer position of the payload, stuff bit information, as well as the payload data from the frames of data received; b) means connected to the extracting means, for storing the payload data within an addressable write/read elastic store module accessible by corresponding write and read addresses, said module having a nominal relative center position representing the nominal difference between the write and read addresses; c) means for reading payload data from the elastic store based upon the read data clock rate, said reading means generating a serial output of said read data; d) means connected to the elastic store, for determining the difference between the write and read addresses (W-R) of the elastic store; e) a lookup table which contains values corresponding to changes in the elastic store write addresses based upon pointer position within the frame and changes in pointer position between frames, for all possible pointer positions within the frame; f) means connected to the pointer position and stuff bit information extracting means and to the lookup table, for digitally high pass filtering the stuff bit information and a value from the lookup table determined by the pointer position within the frame and the change in the pointer position, so that changes in the elastic store write address based upon pointer position Within the frame and changes to the pointer position and the stuff bit information from frame to frame are passed to the output of the filtering means at which said changes then decay exponentially to zero; g) means for subtracting the output of the digital high pass filtering means from the W-R address difference to determine a number representative of the difference between the output of the digital high pass filtering means and the W-R address difference; and h) means for using the representative number to generate the read data clock rate whose frequency is adjusted according to this representative number.

Claim 20

A desynchronizer as defined in claim 17, wherein the digital high pass filtering means comprises a register for storing the value to be output by the filter, a multiplier for receipt of the register value and for multiplying it by a value less than one, and a summer for summing the lookup table value based upon the pointer position, the stuff bit information, and the value from the multiplier output, the result of the summer defining an input to the register.

Claim 21

A desynchronizer as defined in claim 18, wherein the means for using the representative number to generate the read data rate includes means for generating a variable duty cycle signal having a constant frequency, whose duty cycle is proportional to the W-R difference from the elastic store module nominal relative center position, which is used to control the read data clock rate.

Claim 22

A desynchronizer as defined in claim 19, further comprising a threshold comparator module for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a first threshold value and if so, setting a status bit indicative of this occurrence, said status bit communicated with the digital high pass filtering means to increase the bandwidth of said digital high pass filtering means.

Claim 23

A desynchronizer as defined in claim 20, wherein the threshold comparator further comprises means for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a second threshold value greater than the first threshold value, and if so for setting a second status bit which is communicated to the digital high pass filtering means to disable all inputs to said digital high pass filtering means and thereby cause rapid movement of the W-R value back to the nominal relative center position of the elastic store module based upon changes in the pointer and stuff bit information appearing directly at the output of the subtracting means, thereby causing rapid adjustment of the read dam clock rate.

Claim 24

A desynchronizer as defined in claim 21, wherein the threshold means has means for determining if the absolute value of the W-R value as compared to the elastic store nominal relative center position exceeds a third threshold value, and if so to set a third status bit, said status bit communicated to the elastic store module to cause the elastic store module to reset its W-R address to the nominal relative center position.

Claim 25

A desynchronizer as defined in claim 17, wherein each frame comprises a plurality of columns, and wherein the lookup table values are based upon the column of the frame where the change in pointer position between frames has occurred.

Claim 26

A desynchronizer as defined in claim 23, wherein the frame comprises ninety columns with 87 possible pointer positions and wherein the lookup table values are defined by the following table, where a positive change in pointer position is from column n to column n+1, and a negative change in pointer position is from column n to column n-1; ______________________________________ Δ Movement In Elastic Store AVERAGED DATA (IN BITS PER POINTER STEP) Pointer Column Pos. Neg. Position (+) (-) ______________________________________ 4 7.1678 -6.8364 5 7.1701 -7.1697 6 7.1695 -7.1669 7 7.1724 -7.1686 8 7.1707 -7.1715 9 7.1690 -7.1697 10 Movement to 7.1713 -7.1680 ← movement from Column 11 Column 10 to Column 9 11 7.1673 -7.1703 12 7.1730 -7.1663 13 7.1690 -7.1720 14 7.1695 -7.1680 15 7.1678 -7.1686 16 7.1650 -7.1669 17 7.1690 -7.1640 18 7.1730 -7.1680 19 7.1707 -7.1720 20 7.1673 -7.1697 21 7.1707 -7.1663 22 7.1696 -7.1697 23 7.1713 -7.1686 24 7.1713 -7.1703 25 7.1695 -7.1703 26 7.1718 -7.1686 27 7.1690 -7.1709 28 7.1672 -7.1680 29 7.1707 -7.1663 30 6.9378 -7.1609 31 6.9082 -6.9668 32 6.9112 -6.9072 33 7.1632 -6.8889 34 7.1724 -7.1651 35 7.1684 -7.1715 36 7.1724 -7.1674 37 7.1707 -7.1715 38 7.1707 -7.1697 39 7.1695 -7.1697 40 7.1684 -7.1686 41 7.1741 -7.1674 42 7.1678 -7.1732 43 7.1713 -7.1669 44 7.1621 -7.1703 45 7.1684 -7.1611 46 7.1707 -7.1675 47 7.1707 -7.1697 48 7.1690 -7.1698 49 7.1701 -7.1680 50 7.1718 -7.1692 51 7.1684 -7.1709 52 7.1724 -7.1674 53 7.1678 -7.1715 54 7.1724 -7.1669 55 7.1701 -7.1715 56 7.1701 -7.1692 57 7.1684 -7.1692 58 7.1690 -7.1674 59 6.9089 -7.2142 60 6.9107 -6.9061 61 6.9107 -6.9107 62 7.1638 -6.8644 63 7.1724 -7.1657 64 7.1661 -7.1715 65 7.1741 -7.1651 66 7.1701 -7.1732 67 7.1701 -7.1692 68 7.1695 -7.1692 69 7.1707 -7.1686 70 7.1713 -7.1697 71 7.1701 -7.1703 72 7.1701 -7.1692 73 7.1632 -7.1692 74 7.1696 -7.1623 75 7.1655 -7.1686 76 7.1736 -7.1646 77 7.1690 -7.1726 78 7.1707 -7.1680 79 7.1690 -7.1698 80 7.1718 -7.1680 81 7.1718 -7.1709 82 7.1684 -7.1709 83 7.1724 -7.1674 84 7.1678 -7.1715 85 7.1724 -7.1669 86 7.1667 -7.1715 87 7.0537 -7.1890 88 6.9103 -7.0985 89 6.9112 -6.9084 90 6.9061 -6.9112 ______________________________________