Clock signal resynchronizing apparatus

Claim 1

Apparatus for smoothing elastic buffer read/write phase hits of multiple bits comprising, in combination: elastic buffer first means, including data, write address and read address inputs and a data output, for storing data input written to an address provided until output in response to a provided read address; summation second means, including first and second input means and output means, for summing the inputs to a combined output; write counter third means, connected to said first and second means, for supplying write address outputs to said first and second means; phase detector fourth means, connected to said output means of said second means and including feedback means and apparatus clock output means, for providing a smoothed clock output means in response to differences between signals received via said feedback means and from said summation second means; and read counter fifth means, connected between said apparatus clock output means of said fourth means and both the read input of said elastic buffer first means and the feedback input of said fourth means, for supplying a continuous count of the clock signal appearing at the apparatus clock output the fifth means and the fourth means providing the function of a phase locked loop.

Claim 4

The method of smoothing an incoming data signal synchronized clock signal pulse where the data is substantially periodically discontinuous for times longer than the period of a data clock signal pulse and further phase hit adjustments of longer than the period of a data clock signal need to be made on a periodic basis comprising the steps of: a. high-pass filtering phase hit adjustment signals to produce first signals; b. summing said first signals and periodically discontinuous clock signals to produce second signals; c. phase detecting said second signals and a feedback signal to produce a third signal; d. filtering said third signal to generate a fourth signal whose response transform complies with V o /V in =(-K/s)*(1+s/S 1 )/(1+s/S 2 ) where s is the Laplace transform operator and S 1 and S 2 and K are constants; e. controlling a controlled oscillator means with said fourth signal to produce a smoothed clock fifth signal; and f. supplying a feedback signal indicative of the frequency of said fifth signal to be used in the phase detection of step (c).

Claim 5

The method of smoothing an incoming data signal synchronized clock signal pulse where the data is substantially periodically discontinuous for times longer than the period of a data clock signal pulse and further phase hit adjustments of longer than the period of a data clock signal need to be made on a periodic basis comprising the steps of: a. high-pass filtering phase hit adjustment signals to produce first signals; b. summing said first signals and periodically discontinuous clock signals to produce second signals; c. phase detecting said second signals and a feedback signal to produce a third signal; d. filtering said third signal to generate a fourth signal whose response transform complies with V o /V in =(-K/s)*(1+s/S 1 )/(1+s/S 2 ) where s is the Laplace transform operator and S 1 and S 2 and K are constants; e. controlling a controlled oscillator means with said fourth signal to produce a smoothed clock fifth signal; and f. supplying a feedback signal indicative of the frequency of said fifth signal to be used in the phase detection of step (c).

Claim 6

The method of resynchronizing an incoming clock signal ranging about an average frequency and a further correction signal causing phase hit adjustments to the clock signal of longer than the period of a single cycle of said clock signal comprising the steps of: high-pass filtering a phase hit adjustment first signal to produce a second signal; summing said second signal and a periodically discontinuous third signal to produce a fourth signal; and type two second order low-pass filtering said fourth signal as part of a phase lock loop to generate a periodically continuous fifth signal whose frequency is indicative of the sum of said second and third signals.

Claim 7

The method of resynchronizing an incoming clock signal ranging about an average frequency and a further correction signal causing phase hit adjustments to the clock signal of longer than the period of a single cycle of said clock signal comprising the steps of: high-pass filtering a phase hit adjustment first signal to produce a second signal; summing said second signal and a periodically discontinuous third signal to produce a fourth signal; and type two second order low-pass filtering said fourth signal as part of a phase lock loop to generate a periodically continuous fifth signal whose frequency is indicative of the sum of said second and third signals.

Claim 8

The method of resynchronizing data associated with an incoming clock signal ranging about an average frequency and a further correction signal causing phase hit adjustments to the clock signal of longer than the period of a single cycle of said clock signal comprising the steps of: high-pass filtering a phase hit adjustment first signal to produce a second signal; writing data into an elastic buffer in accordance with the occurrence of a clock third signal; summing said second signal and said third signal and phase detecting the result to produce a fourth signal; second order type 2 low-pass filtering said fourth signal to generate a periodically continuous fifth signal whose frequency is indicative of the sum of said second and third signals; and reading data from the elastic buffer in accordance with said fifth signal to produce a periodically continuous data stream.

Claim 9

The method of resynchronizing data associated with an incoming clock signal ranging about an average frequency and a further correction signal causing phase hit adjustments to the clock signal of longer than the period of a single cycle of said clock signal comprising the steps of: high-pass filtering a phase hit adjustment first signal to produce a second signal; writing data into an elastic buffer in accordance with the occurrence of a clock third signal; summing said second signal and said third signal and phase detecting the result to produce a fourth signal; second order type 2 low-pass filtering said fourth signal to generate a periodically continuous fifth signal whose frequency is indicative of the sum of said second and third signals; and reading data from the elastic buffer in accordance with said fifth signal to produce a periodically continuous data stream.