Amplifier with actively clamped load

Claim 2

A semiconductor memory arrangement comprising: an array of storage cells arranged in plural addressable rows and columns; row addressing means, responsive to row address signals, for selecting a row of storage cells; column addressing means, responsive to column address signals, for selecting at least one column of storage cells; a plurality of bit lines, each bit line associated with a column of storage cells; a plurality of sense amplifiers, each sense amplifier associated with a different column of storage cells; and each sense amplifier including an actively clamped load that clamps signal swings across the sense amplifier load in response to a D.C. voltage level and a signal magnitude on the associated bit line.

Claim 3

A data processing system comprising: a data processor; a memory arrangement; an address bus, a data bus, and a control bus interconnecting the data processor with the memory arrangement; the memory arrangement including: a column of storage cells associated with a bit line for reading data from the storage cells; a sense amplifier coupled to the bit line for sensing the data read from the storage cells; and the sense amplifier having an actively clamped load for clamping signal swings across the sense amplifier load in response to a D.C. voltage level and a signal magnitude on the bit line.

Claim 4

A data processing system comprising: a data processor; a memory arrangement; an address bus, a data bus, and a control bus interconnecting the data processor with the memory arrangement; the memory arrangement including: a column of storage cells associated with a bit line for reading data from the storage cells; a sense amplifier coupled to the bit line for sensing the data read from the storage cells; and the sense amplifier having an actively clamped load for clamping signal swings across the sense amplifier load in response to a D.C. voltage level and a signal magnitude on the bit line.

Claim 5

A data processing system comprising: a data processor; a memory arrangement; an address bus, a data bus, and a control bus interconnecting the data processor with the memory arrangement; the memory arrangement including: a column of storage cells associated with a bit line for reading data from the storage cells; a sense amplifier coupled to the bit line for sensing the data read from the storage cells; the sense amplifier having: an actively clamped load for clamping signal swings across its load in response to a D.C. voltage level and a signal magnitude on the bit line; first and second emitter-coupled transistors; a current source connected between the emitters of the first and second emitter-coupled transistors and a reference potential; first and second loads are connected between the respective collector electrodes of the first and second emitter-coupled transistors and a voltage supply; first and second clamping transistors, each has its collector-emitter path connected across a respective one of the loads; and a clamping control circuit, responsive to an input signal, for producing and applying to base electrodes of the first and second clamping transistors variable control signals to clamp output signal swings across the first and second loads.

Claim 6

A data processing system comprising: a data processor; a memory arrangement; an address bus, a data bus, and a control bus interconnecting the data processor with the memory arrangement; the memory arrangement including: a column of storage cells associated with a bit line for reading data from the storage cells; a sense amplifier coupled to the bit line for sensing the data read from the storage cells; the sense amplifier having: an actively clamped load for clamping signal swings across its load in response to a D.C. voltage level and a signal magnitude on the bit line; first and second emitter-coupled transistors; a current source connected between the emitters of the first and second emitter-coupled transistors and a reference potential; first and second loads are connected between the respective collector electrodes of the first and second emitter-coupled transistors and a voltage supply; first and second clamping transistors, each has its collector-emitter path connected across a respective one of the loads; and a clamping control circuit, responsive to an input signal, for producing and applying to base electrodes of the first and second clamping transistors variable control signals to clamp output signal swings across the first and second loads.

Claim 7

A data processing system, in accordance with claim 3, wherein the control signals change with the D.C. voltage level of the input signal.

Claim 8

A data processing system, in accordance with claim 3, wherein the control signals vary with the magnitude of the input signal.

Claim 9

A data processing system, in accordance with claim 3, wherein output signal swings vary in response to the differences in the control signals.

Claim 10

A differential amplifier, in accordance with claim 3, wherein the first and second clamping transistors, when operated, are operated continuously with voltage gain in a linear region of their operating characteristics.

Claim 11

A semiconductor memory arrangement comprising: an array of storage cells arranged in plural addressable rows and columns; row addressing means, responsive to row address signals, for selecting a row of storage cells; column addressing means, responsive to column address signals, for selecting at least one column of storage cells; a plurality of bit lines, each bit line associated with a column of storage cells; a plurality of sense amplifiers, each sense amplifier associated with a different column of storage cells; each sense amplifier including: an actively clamped load that clamps signal swings across its load in response to a D.C. voltage level and a signal magnitude on the associated bit line; first and second emitter-coupled transistors; a current source connected between the emitters of the first and second emitter-coupled transistors and a reference potential; first and second loads are connected between the respective collector electrodes of the first and second emitter-coupled transistors and a voltage supply; first and second clamping transistors, each has its collector-emitter path connected across a respective one of the loads; and a clamping control circuit, responsive to an input signal, for producing and applying to base electrodes of the first and second clamping transistors variable control signals to clamp output signal swings across the first and second loads.

Claim 12

A semiconductor memory arrangement comprising: an array of storage cells arranged in plural addressable rows and columns; row addressing means, responsive to row address signals, for selecting a row of storage cells; column addressing means, responsive to column address signals, for selecting at least one column of storage cells; a plurality of bit lines, each bit line associated with a column of storage cells; a plurality of sense amplifiers, each sense amplifier associated with a different column of storage cells; each sense amplifier including: an actively clamped load that clamps signal swings across its load in response to a D.C. voltage level and a signal magnitude on the associated bit line; first and second emitter-coupled transistors; a current source connected between the emitters of the first and second emitter-coupled transistors and a reference potential; first and second loads are connected between the respective collector electrodes of the first and second emitter-coupled transistors and a voltage supply; first and second clamping transistors, each has its collector-emitter path connected across a respective one of the loads; and a clamping control circuit, responsive to an input signal, for producing and applying to base electrodes of the first and second clamping transistors variable control signals to clamp output signal swings across the first and second loads.

Claim 13

A semiconductor memory arrangement, in accordance with claim 8, wherein the control signals change with the D.C. voltage level of the input signal.

Claim 14

A semiconductor memory arrangement, in accordance with claim 8, wherein the control signals vary with the magnitude of the input signal.

Claim 15

A semiconductor memory arrangement, in accordance with claim 8, wherein output signal swings vary in response to the differences in the control signals.

Claim 16

A differential amplifier, in accordance with claim 8, wherein the first and second clamping transistors, when operated, are operated continuously with voltage gain in a linear region of their operating characteristics.