Video signal data and composite synchronization extraction circuit for on-screen display

Abstract

Abstract A data and synchronization extraction circuit for processing composite video signals containing closed captioning data is disclosed. A dual mode voltage clamp is realized in CMOS technology which includes temperature compensated current sources in the form of complementary current mirrors. A modified version of such current sources is also disclosed which permits trimming of the current after manufacture and packaging. Sync pulses are separated by doubling the amplitude of a composite video signal with an amplifier and comparing the amplified signal with a back porch level derived by a sample-and-hold device. Frequency and phase synchronization is accomplished by a combination of a frequency lock loop and a phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator provides a clean source of timing information for the circuit. The effects of impulse noise in the detection of vertical retrace pulses are eliminated by the use of digital counting circuits which count the requisite number of horizontal synchronization pluses which occur between valid retrace pulse and which block pluses that appear at other times. A slice level for a data line is held by a small on-chip capacitor. Said slice level is periodically encoded. A decoder converts the encoded level back to an analog format during desired intervals.

Inventors

• 👤 Eric B. Berman
• 👤 Apparajan Ganesan
• 👤 William B. H. Jorden
• 👤 Philip R. McLaughlin
• 👤 William Posner

Bibliographic Details