US5404044A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel process interposer (PPI)
Assignee: International Business Machines Corp
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Filing: 1993-11-17
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Granted: 1995-04-04
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Expires: 2013-11-17
Abstract
Abstract A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.
Inventors
- 👤 Richard B. Booth
- 👤 Robert H. Gephard
- 👤 Bradley S. Gremban
- 👤 Janet E. Poetzinger
- 👤 David T. Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:32
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4611; H05K3/4614; H05K3/462; H05K3/36; H05K3/368; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/641; H05K1/00; H05K1/02; H05K1/0272; H05K1/14; H05K1/144; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09436; H05K2201/095; H05K2201/09536; H05K2201/096; H05K2201/09818; H05K2201/09845; H05K2201/10; H05K2201/10227; H05K2201/10378; H05K3/22; H05K3/225; H05K3/30; H05K3/32; H05K3/321; H05K3/40; H05K3/42; H05K3/429; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49128; Y10T29/49155; Y10T29/49165; Y10T29/49718; Y10T29/49721; Y10T29/49723; Y10T29/49725; Y10T29/49726; Y10T29/4973
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
89 words
An integrated circuit chip interposer having a plurality of interposer layers comprised of: a di-electric layer; a first conductive plane on a top surface of said di-electric layer; a second conductive plane on a bottom surface of said di-electric layer; an adhesive layer coating each said conductive plane; a plurality of conductive vias through said di-electric layer; a conductive adhesive in each said via; and said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via.
Claim 2
Dependent Claim
89 words
An integrated circuit chip interposer having a plurality of interposer layers comprised of: a di-electric layer; a first conductive plane on a top surface of said di-electric layer; a second conductive plane on a bottom surface of said di-electric layer; an adhesive layer coating each said conductive plane; a plurality of conductive vias through said di-electric layer; a conductive adhesive in each said via; and said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via.
Claim 3
Dependent Claim
18 words
The integrated circuit chip interposer of claim 1 further comprising a cap at one end of said stack.
Claim 4
Dependent Claim
16 words
The integrated circuit chip interposer of claim 1 wherein said di-electric layer is a polyimide layer.
Claim 5
Dependent Claim
17 words
The integrated circuit chip interposer of claim 1 wherein said first and second conductive planes are copper.
Claim 6
Dependent Claim
30 words
The integrated circuit chip interposer of claim 1 wherein said first conductive plane is a signal distribution plane and said second conductive plane is a power of ground distribution plane.
Claim 7
Dependent Claim
29 words
The interposer of claim 1 wherein said adhesive layer is comprised of a first soluble thermoplastic material and said conductive adhesive is comprised of a second soluble thermoplastic material.
Claim 8
Dependent Claim
98 words
An integrated circuit chip package comprised of: an interposer having a plurality of interposer layers comprised of: a di-electric layer, a conductive plane on a top surface of said di-electric layer, a conductive plane on a bottom surface of said di-electric layer, each said conductive layer being coated by an adhesive coating, a plurality of conductive vias through said di-electric layer, and, a conductive adhesive paste in each said via, said plurality of layers in a stack, said stacked layers being bonded together by said conductive adhesive paste; and, a substrate, said interposer being mounted on said substrate.
Claim 9
Dependent Claim
98 words
An integrated circuit chip package comprised of: an interposer having a plurality of interposer layers comprised of: a di-electric layer, a conductive plane on a top surface of said di-electric layer, a conductive plane on a bottom surface of said di-electric layer, each said conductive layer being coated by an adhesive coating, a plurality of conductive vias through said di-electric layer, and, a conductive adhesive paste in each said via, said plurality of layers in a stack, said stacked layers being bonded together by said conductive adhesive paste; and, a substrate, said interposer being mounted on said substrate.
Claim 10
Dependent Claim
19 words
The integrated circuit chip package of claim 7 further comprising a cap at one end of said interposer stack.
Claim 11
Dependent Claim
17 words
The integrated circuit chip package of claim 7 wherein said interposer's di-electric layer is a polyimide layer.
Claim 12
Dependent Claim
18 words
The integrated circuit chip package of claim 7 wherein said first and said second conductive planes are copper.
Claim 13
Dependent Claim
30 words
The integrated circuit chip interposer of claim 7 wherein said first conductive plane is a signal distribution plane and said second conductive plane is a power or ground distribution plane.
References Cited (Backward Citations)
US4050756A
Cited
US4383363A
Cited
US4268956A
Cited
US4191789A
Cited
US4322778A
Cited
US4318954A
Cited
US4438561A
Cited
US4617730A
Cited
US4713494A
Cited
US4811082A
Cited
US4788767A
Cited
US4908940A
Cited
US4935584A
Cited
US5030800A
Cited
US5065228A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |