Patent US2961862A successfully refreshed from Google Patents.
Patent US5404042A successfully refreshed from Google Patents.
US5404042A
Expired / Lapsed
US
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Semiconductor memory device having a plurality of well regions of different conductivities
Assignee: Renesas Electronics Corp
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Filing: 1993-06-04
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Granted: 1995-04-04
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Expires: 2013-06-04
Abstract
Abstract A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.
Inventors
- 👤 Yoshinori Okumura
- 👤 Tomonori Okudaira
- 👤 Hideaki Arima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:09
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
310 words
A semiconductor memory device, comprising: a p type semiconductor substrate having a main surface and including a memory cell array region in which a memory cell array, including a memory portion having a plurality of memory cells and associated memory active elements arranged on the main surface and a circuit portion having a plurality of peripheral active elements connected to the memory cell portion and performing an access operation for writing/reading storage information, is formed, and a peripheral circuit region in which circuit portions other than said memory cell array are formed; a first p well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a first set of said peripheral active elements and connected to an input terminal for receiving an external input signal, and having a potential held at a ground potential; a first n well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a second set of said peripheral active elements and having a potential held at a positive potential; a second p well region formed in said semiconductor substrate in said memory cell array region so as to surround a first set of said memory cells and associated memory active elements and having a potential held at one of a negative potential and the ground potential; a second n well region formed in said semiconductor substrate in said memory cell array region so as to surround a second set of said memory cells and associated memory active elements and having a potential held at the positive potential; and a third n well region formed in said semiconductor substrate to surround said second p well region and said second n well region and having a potential held at the positive potential, said third n well region being doped differently from said second n region.
Claim 2
Dependent Claim
310 words
A semiconductor memory device, comprising: a p type semiconductor substrate having a main surface and including a memory cell array region in which a memory cell array, including a memory portion having a plurality of memory cells and associated memory active elements arranged on the main surface and a circuit portion having a plurality of peripheral active elements connected to the memory cell portion and performing an access operation for writing/reading storage information, is formed, and a peripheral circuit region in which circuit portions other than said memory cell array are formed; a first p well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a first set of said peripheral active elements and connected to an input terminal for receiving an external input signal, and having a potential held at a ground potential; a first n well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a second set of said peripheral active elements and having a potential held at a positive potential; a second p well region formed in said semiconductor substrate in said memory cell array region so as to surround a first set of said memory cells and associated memory active elements and having a potential held at one of a negative potential and the ground potential; a second n well region formed in said semiconductor substrate in said memory cell array region so as to surround a second set of said memory cells and associated memory active elements and having a potential held at the positive potential; and a third n well region formed in said semiconductor substrate to surround said second p well region and said second n well region and having a potential held at the positive potential, said third n well region being doped differently from said second n region.
Claim 3
Dependent Claim
311 words
A semiconductor memory device, comprising: a p type semiconductor substrate having a main surface and including a memory cell array region in which a memory cell array, including a memory cell portion having a plurality of memory cells and associated memory active elements arranged on the main surface and a circuit portion having a plurality of peripheral active elements connected to the memory cell portion and performing an access operation for writing/reading storage information, is formed, and a peripheral circuit region in which circuit portions other than said memory cell array are formed; a first p well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a first set of said peripheral active elements and connected to an input terminal for receiving an external input signal, and having a potential held at a ground potential; a first n well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a second set of said peripheral active elements and having a potential held at a positive potential; a second p well region formed in said semiconductor substrate in said memory cell array region so as to surround a first set of said memory cells add associated memory active elements and having a potential held at one of a negative potential and the ground potential; a second n well region formed in said semiconductor substrate in said memory cell array region so as to surround a second set of said memory cells and associated memory active elements and having a potential held at the positive potential; and a third n well region formed in said semiconductor substrate to surround said first p well region and said first n well region and having a potential held at the positive potential, said third n well region being doped differently from said first n region.
Claim 4
Dependent Claim
311 words
A semiconductor memory device, comprising: a p type semiconductor substrate having a main surface and including a memory cell array region in which a memory cell array, including a memory cell portion having a plurality of memory cells and associated memory active elements arranged on the main surface and a circuit portion having a plurality of peripheral active elements connected to the memory cell portion and performing an access operation for writing/reading storage information, is formed, and a peripheral circuit region in which circuit portions other than said memory cell array are formed; a first p well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a first set of said peripheral active elements and connected to an input terminal for receiving an external input signal, and having a potential held at a ground potential; a first n well region formed in said semiconductor substrate in said peripheral circuit region so as to surround a second set of said peripheral active elements and having a potential held at a positive potential; a second p well region formed in said semiconductor substrate in said memory cell array region so as to surround a first set of said memory cells add associated memory active elements and having a potential held at one of a negative potential and the ground potential; a second n well region formed in said semiconductor substrate in said memory cell array region so as to surround a second set of said memory cells and associated memory active elements and having a potential held at the positive potential; and a third n well region formed in said semiconductor substrate to surround said first p well region and said first n well region and having a potential held at the positive potential, said third n well region being doped differently from said first n region.
Claim 5
Dependent Claim
22 words
The device of claim 1, wherein said second p well region and said second n well region are separated from each other.
Claim 6
Dependent Claim
22 words
The device of claim 2, wherein said first p well region and said first n well region are separated from each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |