Application specific integrated circuit and placement and routing software with non-customizable first metal layer and vias and customizable second metal grid pattern

Claim 2

A gate array integrated circuit for subsequent customization of an included integrated circuit (IC) with a single-etch of a second metal layer, comprising: a plurality of identical basic cells arranged into rows columns within said IC wherein each basic cell includes a diffusion of four transistors; a non-exposed first metallization layer including a plurality of non-intersecting connective strips that are electrically connected to the basic cells by a plurality of contacts; and a second metallization layer exposed on a surface of said IC for providing for susceptibility to subsequent customization by metal etching and including an orthogonal mesh of conductors that are electrically connected to corresponding said connective strips by a plurality of vias positioned at respective intersections of said mesh of conductors and having a first plurality of evenly spaced uniform small openings between a first plurality of intersections of said mesh of conductors and a first plurality of conductive links between a second plurality of intersections of said mesh of conductors that connect each one of said intersections to less than all of a set of corresponding surrounding adjacent intersections in said first plurality of intersections.

Claim 3

The IC of claim 1, wherein: the second metallization layer includes openings in said orthogonal mesh of conductors that isolate portions of the basic cell.

Claim 4

The IC of claim 1, wherein: the second metallization layer includes a plurality of notches in openings in said orthogonal mesh of conductors for minimization of the size of the basic cell.

Claim 5

A customizable gate array integrated circuit (IC) system, comprising: a plurality of identical basic cells arranged into rows and columns within said IC wherein each basic cell includes a diffusion of four transistors in a common semiconductor substrate; a non-exposed first metallization layer including a plurality of non-intersecting connective strips that are electrically connected to respective basic cells by a corresponding plurality of contacts; a second metallization layer disposed on a surface of said IC for providing for susceptibility to subsequent customization by metal etching and including an orthogonal mesh of conductors that are electrically connected to corresponding said connective strips by a plurality of vias positioned at respective intersections of said mesh of conductors and having a first plurality of evenly spaced uniform small openings between a first plurality of intersections of said mesh of conductors and a first plurality of conductive links between a second plurality of intersections of said mesh of conductors that connect each one of said intersections to less than all of a set of corresponding surrounding adjacent intersections in said first plurality of intersections; a thin oxide passivation layer overlying the second metallization layer and providing for handling and transportation scratch prevention and constituted to be subsequently removable by a global oxide etch; and a plurality of global routing channels including etch-links that interconnect the plurality of basic cells.

Claim 6

A customizable gate array integrated circuit (IC) system, comprising: a plurality of identical basic cells arranged into rows and columns within said IC wherein each basic cell includes a diffusion of four transistors in a common semiconductor substrate; a non-exposed first metallization layer including a plurality of non-intersecting connective strips that are electrically connected to respective basic cells by a corresponding plurality of contacts; a second metallization layer disposed on a surface of said IC for providing for susceptibility to subsequent customization by metal etching and including an orthogonal mesh of conductors that are electrically connected to corresponding said connective strips by a plurality of vias positioned at respective intersections of said mesh of conductors and having a first plurality of evenly spaced uniform small openings between a first plurality of intersections of said mesh of conductors and a first plurality of conductive links between a second plurality of intersections of said mesh of conductors that connect each one of said intersections to less than all of a set of corresponding surrounding adjacent intersections in said first plurality of intersections; a thin oxide passivation layer overlying the second metallization layer and providing for handling and transportation scratch prevention and constituted to be subsequently removable by a global oxide etch; and a plurality of global routing channels including etch-links that interconnect the plurality of basic cells.

Claim 7

The system of claim 4, further comprising: computer programming software on a disk for computer-aided design (CAD) that includes computer instructions for: translating a user or third party design interconnect netlist; allowing a user to control the placement and locations of bonding pads and input/output (I/O) cells to duplicate an original design; automatically placing the locations of core cells based on said I/O cell locations and to minimize wire length and timing delays; global control of the routing resource such that a later channel routing becomes feasible, wherein a maze routing technique is used which does not allow input pins to be simultaneously accessed; channel routing of the second metallization layer; and final verification in which any routed data is extracted into a netlist form and compared against an original netlist to ensure data consistency.

Claim 8

A gate array integrated circuit system for subsequent customization of an included integrated circuit (IC) with a single-etch of a second metal layer, comprising: a plurality of identical basic cells arranged into rows and columns within said IC wherein each basic cell includes a diffusion of four transistors; a non-exposed first metallization layer including a plurality of non-intersecting connective strips that are electrically connected to the basic cell by a plurality of contacts; a second metallization layer exposed on a surface of said IC for providing for susceptibility to subsequent customization by metal etching and including an orthogonal mesh of conductors that are electrically connected to corresponding said connective strips by a plurality of vias positioned at respective intersections of said mesh of conductors and having a first plurality of evenly spaced uniform small openings between a first plurality of intersections of said mesh of conductors and a first plurality of conductive links between a second plurality of intersections of said mesh of conductors that connect each one of said intersections to less than all of a set of corresponding surrounding adjacent intersections in said first plurality of intersections; and computer programming software on a disk providing for a patterning of only the second metallization layer by selective etching and including a computer-implemented process for inputting a design netlist and translating said design into a list of said first plurality of conductive links are to be etched-open between said second plurality of intersections in said mesh of conductors.

Claim 9

A gate array integrated circuit system for subsequent customization of an included integrated circuit (IC) with a single-etch of a second metal layer, comprising: a plurality of identical basic cells arranged into rows and columns within said IC wherein each basic cell includes a diffusion of four transistors; a non-exposed first metallization layer including a plurality of non-intersecting connective strips that are electrically connected to the basic cell by a plurality of contacts; a second metallization layer exposed on a surface of said IC for providing for susceptibility to subsequent customization by metal etching and including an orthogonal mesh of conductors that are electrically connected to corresponding said connective strips by a plurality of vias positioned at respective intersections of said mesh of conductors and having a first plurality of evenly spaced uniform small openings between a first plurality of intersections of said mesh of conductors and a first plurality of conductive links between a second plurality of intersections of said mesh of conductors that connect each one of said intersections to less than all of a set of corresponding surrounding adjacent intersections in said first plurality of intersections; and computer programming software on a disk providing for a patterning of only the second metallization layer by selective etching and including a computer-implemented process for inputting a design netlist and translating said design into a list of said first plurality of conductive links are to be etched-open between said second plurality of intersections in said mesh of conductors.

Claim 10

The system of claim 6, wherein: the computer programming software on disk further comprises computer-implemented process means for core cell placement of the basic cells, global routing of second metallization connections amongst the basic cells, channel routing between the basic cells and final verification of the circuit functionality of the basic cells interconnected by said etched and patterned second metallization layer for a customization of said IC according to said design netlist.